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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4C.mail.protection.outlook.com (10.167.242.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Wed, 23 Oct 2024 17:22:19 +0000 Received: from purico-9eb2host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 23 Oct 2024 12:22:15 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , , , , , , , , , , Yazen Ghannam Subject: [PATCH 14/16] x86/amd_smn, platform/x86/amd/hsmp: Have HSMP use SMN Date: Wed, 23 Oct 2024 17:21:48 +0000 Message-ID: <20241023172150.659002-15-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241023172150.659002-1-yazen.ghannam@amd.com> References: <20241023172150.659002-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4C:EE_|PH8PR12MB8429:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d798d64-b4e9-4f99-d6db-08dcf3873fe1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 17:22:19.6886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d798d64-b4e9-4f99-d6db-08dcf3873fe1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8429 The HSMP interface is just an SMN interface with different offsets. Define an HSMP wrapper in the SMN code and have the HSMP platform driver use that rather than a local solution. Also, remove the "root" member from AMD_NB, since there are no more users of it. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/amd_nb.h | 1 - arch/x86/include/asm/amd_smn.h | 3 +++ arch/x86/kernel/amd_nb.c | 1 - arch/x86/kernel/amd_smn.c | 9 +++++++++ drivers/platform/x86/amd/Kconfig | 2 +- drivers/platform/x86/amd/hsmp.c | 32 +++++--------------------------- 6 files changed, 18 insertions(+), 30 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 55c03d3495bc..cbe31e316e39 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -27,7 +27,6 @@ struct amd_l3_cache { }; struct amd_northbridge { - struct pci_dev *root; struct pci_dev *misc; struct pci_dev *link; struct amd_l3_cache l3_cache; diff --git a/arch/x86/include/asm/amd_smn.h b/arch/x86/include/asm/amd_smn.h index 6850de69f863..f0eb12859c42 100644 --- a/arch/x86/include/asm/amd_smn.h +++ b/arch/x86/include/asm/amd_smn.h @@ -8,4 +8,7 @@ int __must_check amd_smn_read(u16 node, u32 address, u32 *value); int __must_check amd_smn_write(u16 node, u32 address, u32 value); +/* Should only be used by the HSMP driver. */ +int __must_check amd_smn_hsmp_rdwr(u16 node, u32 address, u32 *value, bool write); + #endif /* _ASM_X86_AMD_SMN_H */ diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 10cdeddeda02..4c22317a6dfe 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -73,7 +73,6 @@ static int amd_cache_northbridges(void) amd_northbridges.nb = nb; for (i = 0; i < amd_northbridges.num; i++) { - node_to_amd_nb(i)->root = amd_node_get_root(i); node_to_amd_nb(i)->misc = amd_node_get_func(i, 3); node_to_amd_nb(i)->link = amd_node_get_func(i, 4); } diff --git a/arch/x86/kernel/amd_smn.c b/arch/x86/kernel/amd_smn.c index 997fd3edd9c0..527dda8e3a2b 100644 --- a/arch/x86/kernel/amd_smn.c +++ b/arch/x86/kernel/amd_smn.c @@ -18,6 +18,9 @@ static DEFINE_MUTEX(smn_mutex); #define SMN_INDEX_OFFSET 0x60 #define SMN_DATA_OFFSET 0x64 +#define HSMP_INDEX_OFFSET 0xc4 +#define HSMP_DATA_OFFSET 0xc8 + /* * SMN accesses may fail in ways that are difficult to detect here in the called * functions amd_smn_read() and amd_smn_write(). Therefore, callers must do @@ -100,6 +103,12 @@ int __must_check amd_smn_write(u16 node, u32 address, u32 value) } EXPORT_SYMBOL_GPL(amd_smn_write); +int __must_check amd_smn_hsmp_rdwr(u16 node, u32 address, u32 *value, bool write) +{ + return __amd_smn_rw(HSMP_INDEX_OFFSET, HSMP_DATA_OFFSET, node, address, value, write); +} +EXPORT_SYMBOL_GPL(amd_smn_hsmp_rdwr); + static int amd_cache_roots(void) { u16 node, num_nodes = amd_num_nodes(); diff --git a/drivers/platform/x86/amd/Kconfig b/drivers/platform/x86/amd/Kconfig index f88682d36447..e100b315c62b 100644 --- a/drivers/platform/x86/amd/Kconfig +++ b/drivers/platform/x86/amd/Kconfig @@ -8,7 +8,7 @@ source "drivers/platform/x86/amd/pmc/Kconfig" config AMD_HSMP tristate "AMD HSMP Driver" - depends on AMD_NB && X86_64 && ACPI + depends on AMD_SMN && X86_64 && ACPI help The driver provides a way for user space tools to monitor and manage system management functionality on EPYC server CPUs from AMD. diff --git a/drivers/platform/x86/amd/hsmp.c b/drivers/platform/x86/amd/hsmp.c index 8fcf38eed7f0..544efb0255c0 100644 --- a/drivers/platform/x86/amd/hsmp.c +++ b/drivers/platform/x86/amd/hsmp.c @@ -10,7 +10,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include -#include +#include #include #include #include @@ -48,9 +48,6 @@ #define SMN_HSMP_MSG_RESP 0x0010980 #define SMN_HSMP_MSG_DATA 0x00109E0 -#define HSMP_INDEX_REG 0xc4 -#define HSMP_DATA_REG 0xc8 - #define HSMP_CDEV_NAME "hsmp_cdev" #define HSMP_DEVNODE_NAME "hsmp" #define HSMP_METRICS_TABLE_NAME "metrics_bin" @@ -62,8 +59,6 @@ #define MSG_ARGOFF_STR "MsgArgOffset" #define MSG_RESPOFF_STR "MsgRspOffset" -#define MAX_AMD_SOCKETS 8 - struct hsmp_mbaddr_info { u32 base_addr; u32 msg_id_off; @@ -79,7 +74,6 @@ struct hsmp_socket { void __iomem *virt_base_addr; struct semaphore hsmp_sem; char name[HSMP_ATTR_GRP_NAME_SIZE]; - struct pci_dev *root; struct device *dev; u16 sock_ind; }; @@ -98,20 +92,7 @@ static struct hsmp_plat_device plat_dev; static int amd_hsmp_pci_rdwr(struct hsmp_socket *sock, u32 offset, u32 *value, bool write) { - int ret; - - if (!sock->root) - return -ENODEV; - - ret = pci_write_config_dword(sock->root, HSMP_INDEX_REG, - sock->mbinfo.base_addr + offset); - if (ret) - return ret; - - ret = (write ? pci_write_config_dword(sock->root, HSMP_DATA_REG, *value) - : pci_read_config_dword(sock->root, HSMP_DATA_REG, value)); - - return ret; + return amd_smn_hsmp_rdwr(sock->sock_ind, sock->mbinfo.base_addr + offset, value, write); } static void amd_hsmp_acpi_rdwr(struct hsmp_socket *sock, u32 offset, @@ -749,10 +730,7 @@ static int init_platform_device(struct device *dev) int ret, i; for (i = 0; i < plat_dev.num_sockets; i++) { - if (!node_to_amd_nb(i)) - return -ENODEV; sock = &plat_dev.sock[i]; - sock->root = node_to_amd_nb(i)->root; sock->sock_ind = i; sock->dev = dev; sock->mbinfo.base_addr = SMN_HSMP_BASE; @@ -946,11 +924,11 @@ static int __init hsmp_plt_init(void) int ret = -ENODEV; /* - * amd_nb_num() returns number of SMN/DF interfaces present in the system + * amd_num_nodes() returns number of SMN/DF interfaces present in the system * if we have N SMN/DF interfaces that ideally means N sockets */ - plat_dev.num_sockets = amd_nb_num(); - if (plat_dev.num_sockets == 0 || plat_dev.num_sockets > MAX_AMD_SOCKETS) + plat_dev.num_sockets = amd_num_nodes(); + if (plat_dev.num_sockets == 0 || plat_dev.num_sockets > MAX_AMD_NUM_NODES) return ret; ret = platform_driver_register(&amd_hsmp_driver);