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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF00006001.mail.protection.outlook.com (10.167.243.233) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.11 via Frontend Transport; Tue, 23 Jul 2024 17:36:11 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 23 Jul 2024 12:36:09 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH 0/5] Introduce initial AMD I3C HCI driver support Date: Tue, 23 Jul 2024 23:05:33 +0530 Message-ID: <20240723173538.3493935-1-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00006001:EE_|PH7PR12MB7330:EE_ X-MS-Office365-Filtering-Correlation-Id: 74d2f8b7-86b8-4184-8a50-08dcab3df223 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2024 17:36:11.9475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74d2f8b7-86b8-4184-8a50-08dcab3df223 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00006001.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7330 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240723_103625_168621_56F80D0E X-CRM114-Status: GOOD ( 11.36 ) X-Mailman-Approved-At: Tue, 23 Jul 2024 16:46:53 -0700 X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The AMD SoC includes an I3C IP block as part of the Fusion Controller Hub (FCH). This series introduces the initial driver support to enable the I3C IP block on AMD's latest processors. Currently, the code is closely tied to dt-bindings. This initial set aims to decouple some of these bindings by adding the MIPI ID, allowing the current driver to support ACPI-enabled x86 systems. It was discovered that the AMD I3C controller has several hardware issues, including: - Non-functional DMA mode (defaulting to PIO mode) - Issues with Open-Drain (OD) and Push-Pull (PP) timing parameters - Command response buffer threshold values All of these issues have been addressed in this series. Shyam Sundar S K (5): i3c: mipi-i3c-hci: Add MIPI0100 ACPI ID to the I3C Support List i3c: mipi-i3c-hci: Add a quirk to set PIO mode i3c: mipi-i3c-hci: Relocate helper macros to HCI header file i3c: mipi-i3c-hci: Add a quirk to set timing parameters i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold drivers/i3c/master/mipi-i3c-hci/Makefile | 3 +- drivers/i3c/master/mipi-i3c-hci/core.c | 34 ++++++++++--- drivers/i3c/master/mipi-i3c-hci/hci.h | 11 ++++ drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 53 ++++++++++++++++++++ 4 files changed, 94 insertions(+), 7 deletions(-) create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks.c