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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002BA51.mail.protection.outlook.com (10.167.242.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7828.19 via Frontend Transport; Tue, 6 Aug 2024 07:59:08 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 6 Aug 2024 02:59:03 -0500 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: Guruvendra Punugupati , Krishnamoorthi M , , , Shyam Sundar S K Subject: [PATCH v3 0/5] Introduce initial AMD I3C HCI driver support Date: Tue, 6 Aug 2024 13:28:38 +0530 Message-ID: <20240806075843.277969-1-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|MW4PR12MB7285:EE_ X-MS-Office365-Filtering-Correlation-Id: d923079c-1d5a-4766-7823-08dcb5eda649 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2024 07:59:08.0695 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d923079c-1d5a-4766-7823-08dcb5eda649 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7285 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240806_005918_164636_75AE3766 X-CRM114-Status: GOOD ( 12.05 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org The AMD SoC includes an I3C IP block as part of the Fusion Controller Hub (FCH). This series introduces the initial driver support to enable the I3C IP block on AMD's latest processors. Currently, the code is closely tied to dt-bindings. This initial set aims to decouple some of these bindings by adding the MIPI ID, allowing the current driver to support ACPI-enabled x86 systems. It was discovered that the AMD I3C controller has several hardware issues, including: - Non-functional DMA mode (defaulting to PIO mode) - Issues with Open-Drain (OD) and Push-Pull (PP) timing parameters - Command response buffer threshold values All of these issues have been addressed in this series. v2->v3: ------- - use MODULE_DEVICE_TABLE() - realign patches - address remarks from Jarkko v1->v2: ------- - Address LKP reported problems - Guard boot_cpu_data usage with CONFIG_X86 Shyam Sundar S K (5): i3c: mipi-i3c-hci: Add MIPI0100 ACPI ID to the I3C Support List i3c: mipi-i3c-hci: Add a quirk to set PIO mode i3c: mipi-i3c-hci: Relocate helper macros to HCI header file i3c: mipi-i3c-hci: Add a quirk to set timing parameters i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold drivers/i3c/master/mipi-i3c-hci/Makefile | 3 +- drivers/i3c/master/mipi-i3c-hci/core.c | 36 ++++++++++--- drivers/i3c/master/mipi-i3c-hci/hci.h | 12 +++++ drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 55 ++++++++++++++++++++ 4 files changed, 98 insertions(+), 8 deletions(-) create mode 100644 drivers/i3c/master/mipi-i3c-hci/hci_quirks.c