mbox series

[v4,0/3] Fix i2c and i3c scl rate according bus mode

Message ID cover.1560968688.git.vitor.soares@synopsys.com (mailing list archive)
Headers show
Series Fix i2c and i3c scl rate according bus mode | expand

Message

Vitor Soares June 19, 2019, 6:36 p.m. UTC 
This patch series fix the i2c and i3c scl rate according the bus mode
and LVR register. It also introduce the mixed limited bus for the
cases where i2c devices doesn't have 50 ns filter but allow higher
clock rate for i3c transfers.
Please refer table 5 and 10 of i3c bus spec v1.0 for more detail.

Please follow each patch commit message for more details and changes
made in this version.

Vitor Soares (3):
  i3c: fix i2c and i3c scl rate by bus mode
  i3c: add mixed limited bus mode
  i3c: dw: add limited bus mode support

 drivers/i3c/master.c               | 57 +++++++++++++++++++++++++++++---------
 drivers/i3c/master/dw-i3c-master.c |  1 +
 include/linux/i3c/master.h         |  5 ++++
 3 files changed, 50 insertions(+), 13 deletions(-)

Comments

Boris Brezillon June 20, 2019, 8:56 a.m. UTC | #1 
On Wed, 19 Jun 2019 20:36:30 +0200
Vitor Soares <Vitor.Soares@synopsys.com> wrote:

> This patch series fix the i2c and i3c scl rate according the bus mode
> and LVR register. It also introduce the mixed limited bus for the
> cases where i2c devices doesn't have 50 ns filter but allow higher
> clock rate for i3c transfers.
> Please refer table 5 and 10 of i3c bus spec v1.0 for more detail.
> 
> Please follow each patch commit message for more details and changes
> made in this version.
> 
> Vitor Soares (3):
>   i3c: fix i2c and i3c scl rate by bus mode
>   i3c: add mixed limited bus mode
>   i3c: dw: add limited bus mode support

Queued to i3c/next.

Thanks,

Boris

> 
>  drivers/i3c/master.c               | 57 +++++++++++++++++++++++++++++---------
>  drivers/i3c/master/dw-i3c-master.c |  1 +
>  include/linux/i3c/master.h         |  5 ++++
>  3 files changed, 50 insertions(+), 13 deletions(-)
>