| Message ID | 20190310135843.21154-5-pgaj@cadence.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add the I3C mastership request | expand |
On Sun, 10 Mar 2019 13:58:41 +0000 Przemyslaw Gaj <pgaj@cadence.com> wrote: > This patch adds support for mastership request to Cadence I3C master driver. > > Mastership is requested automatically after secondary master > receives mastership ENEC event. This allows secondary masters to > initialize their bus. > > Signed-off-by: Przemyslaw Gaj <pgaj@cadence.com> > > --- > > Main changes between v3 and v4: > - Refactored the code > > Main changes between v2 and v3: > - Add mastership type > - Add postponed master registration > - Add update device definition on bus initialization time > - Removed redundant mastership work structs > - Reworked IBI slot lookup > - Reworked Mastership event enabling/disabling > > Changes in v2: > - Add work structs for mastership purpose > - Add missing mastership disable feature > --- > drivers/i3c/master/i3c-master-cdns.c | 495 +++++++++++++++++++++++++++++++---- > 1 file changed, 443 insertions(+), 52 deletions(-) > > diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c > index 237f24a..61d6416 100644 > --- a/drivers/i3c/master/i3c-master-cdns.c > +++ b/drivers/i3c/master/i3c-master-cdns.c > @@ -157,6 +157,7 @@ > #define SLV_IMR 0x48 > #define SLV_ICR 0x4c > #define SLV_ISR 0x50 > +#define SLV_INT_DEFSLVS BIT(21) > #define SLV_INT_TM BIT(20) > #define SLV_INT_ERROR BIT(19) > #define SLV_INT_EVENT_UP BIT(18) > @@ -388,8 +389,19 @@ struct cdns_i3c_xfer { > struct cdns_i3c_cmd cmds[0]; > }; > > +enum cdns_i3c_mr { > + REQUEST, > + HANDOFF, > + TAKEOVER > +}; > + > struct cdns_i3c_master { > struct work_struct hj_work; > + struct { > + struct work_struct work; > + enum cdns_i3c_mr mr_type; > + u32 ibir; > + } mastership; > struct i3c_master_controller base; > u32 free_rr_slots; > unsigned int maxdevs; > @@ -408,6 +420,8 @@ struct cdns_i3c_master { > struct clk *pclk; > struct cdns_i3c_master_caps caps; > unsigned long i3c_scl_lim; > + struct device *parent; > + struct workqueue_struct *wq; > }; > > static inline struct cdns_i3c_master * > @@ -663,6 +677,88 @@ static void cdns_i3c_master_unqueue_xfer(struct cdns_i3c_master *master, > spin_unlock_irqrestore(&master->xferqueue.lock, flags); > } > > +static void > +cdns_i3c_master_i3c_dev_rr_to_info(struct cdns_i3c_master *master, cdns_i3c_master_dev_rr_to_i3c_info(... > + unsigned int slot, > + struct i3c_device_info *info) > +{ > + u32 rr; > + > + memset(info, 0, sizeof(*info)); > + rr = readl(master->regs + DEV_ID_RR0(slot)); > + info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr); > + rr = readl(master->regs + DEV_ID_RR2(slot)); > + info->dcr = rr; > + info->bcr = rr >> 8; > + info->pid = rr >> 16; > + info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16; > +} > + > +static void > +cdns_i3c_master_i2c_dev_rr_to_info(struct cdns_i3c_master *master, cdns_i3c_master_dev_rr_to_i2c_info(... > + unsigned int slot, > + u16 *addr, u8 *lvr) > +{ > + u32 rr; > + > + rr = readl(master->regs + DEV_ID_RR0(slot)); > + *addr = DEV_ID_RR0_GET_DEV_ADDR(rr); > + rr = readl(master->regs + DEV_ID_RR2(slot)); > + *lvr = rr; > +} > + > +static > +int cdns_i3c_sec_master_request_mastership(struct i3c_master_controller *m) It's also used for the primary master to get ownership back, right? In that case, don't prefix things with _sec_master. > +{ > + struct cdns_i3c_master *master = to_cdns_i3c_master(m); > + u32 status; > + int ret; > + > + status = readl(master->regs + MST_STATUS0); > + if (WARN_ON(status & MST_STATUS0_MASTER_MODE)) > + return -EEXIST; > + > + status = readl(master->regs + SLV_STATUS1); > + if (status & SLV_STATUS1_MR_DIS) > + return -EACCES; > + > + writel(SLV_INT_MR_DONE, master->regs + SLV_IER); Hm, you seem to poll the master mode status, what's the point of enabling this interrupt? > + writel(readl(master->regs + CTRL) | CTRL_MST_INIT | CTRL_MST_ACK, > + master->regs + CTRL); > + > + ret = readl_poll_timeout(master->regs + MST_STATUS0, status, > + status & MST_STATUS0_MASTER_MODE, 100, > + 100000); > + return ret; > +} > + > +static void cdns_i3c_master_update_devs(struct i3c_master_controller *m) > +{ > + struct cdns_i3c_master *master = to_cdns_i3c_master(m); > + u32 val, newdevs; > + u16 addr; > + u8 lvr; > + int slot; > + struct i3c_device_info i3c_info; > + > + newdevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK; > + for (slot = 1; slot <= master->maxdevs; slot++) { > + val = readl(master->regs + DEV_ID_RR0(slot)); > + > + if ((newdevs & BIT(slot)) && (val & DEV_ID_RR0_IS_I3C)) { > + cdns_i3c_master_i3c_dev_rr_to_info(master, slot, > + &i3c_info); > + > + i3c_master_add_i3c_dev_locked(m, i3c_info.dyn_addr); > + } else if ((newdevs & BIT(slot)) && > + !(val & DEV_ID_RR0_IS_I3C)) { > + cdns_i3c_master_i2c_dev_rr_to_info(master, slot, > + &addr, &lvr); > + i3c_master_add_i2c_dev(m, addr, lvr); > + } > + } > +} > + > static enum i3c_error_code cdns_i3c_cmd_get_err(struct cdns_i3c_cmd *cmd) > { > switch (cmd->error) { > @@ -913,6 +1009,7 @@ static int cdns_i3c_master_get_rr_slot(struct cdns_i3c_master *master, > return ffs(master->free_rr_slots) - 1; > } > > + > activedevs = readl(master->regs + DEVS_CTRL) & > DEVS_CTRL_DEVS_ACTIVE_MASK; > > @@ -1005,9 +1102,9 @@ static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) > master->free_rr_slots &= ~BIT(slot); > i2c_dev_set_master_data(dev, data); > > - writel(prepare_rr0_dev_address(dev->boardinfo->base.addr), > + writel(prepare_rr0_dev_address(dev->addr), > master->regs + DEV_ID_RR0(data->id)); > - writel(dev->boardinfo->lvr, master->regs + DEV_ID_RR2(data->id)); > + writel(dev->lvr, master->regs + DEV_ID_RR2(data->id)); > writel(readl(master->regs + DEVS_CTRL) | > DEVS_CTRL_DEV_ACTIVE(data->id), > master->regs + DEVS_CTRL); Should be part of patch 1, and you need to patch the designware driver too. > @@ -1037,22 +1134,6 @@ static void cdns_i3c_master_bus_cleanup(struct i3c_master_controller *m) > cdns_i3c_master_disable(master); > } > > -static void cdns_i3c_master_dev_rr_to_info(struct cdns_i3c_master *master, > - unsigned int slot, > - struct i3c_device_info *info) > -{ > - u32 rr; > - > - memset(info, 0, sizeof(*info)); > - rr = readl(master->regs + DEV_ID_RR0(slot)); > - info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr); > - rr = readl(master->regs + DEV_ID_RR2(slot)); > - info->dcr = rr; > - info->bcr = rr >> 8; > - info->pid = rr >> 16; > - info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16; > -} > - > static void cdns_i3c_master_upd_i3c_scl_lim(struct cdns_i3c_master *master) > { > struct i3c_master_controller *m = &master->base; > @@ -1180,10 +1261,6 @@ static int cdns_i3c_master_do_daa(struct i3c_master_controller *m) > > cdns_i3c_master_upd_i3c_scl_lim(master); > > - /* Unmask Hot-Join and Mastership request interrupts. */ > - i3c_master_enec_locked(m, I3C_BROADCAST_ADDR, > - I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR); > - > return 0; > } > > @@ -1247,15 +1324,17 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) > prescl1 = PRESCL_CTRL1_OD_LOW(ncycles); > writel(prescl1, master->regs + PRESCL_CTRL1); > > - /* Get an address for the master. */ > - ret = i3c_master_get_free_addr(m, 0); > - if (ret < 0) > - return ret; > + if (!m->secondary) { > + /* Get an address for the master. */ > + ret = i3c_master_get_free_addr(m, 0); > + if (ret < 0) > + return ret; > > - writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C, > - master->regs + DEV_ID_RR0(0)); > + writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C, > + master->regs + DEV_ID_RR0(0)); > + } > > - cdns_i3c_master_dev_rr_to_info(master, 0, &info); > + cdns_i3c_master_i3c_dev_rr_to_info(master, 0, &info); > if (info.bcr & I3C_BCR_HDR_CAP) > info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR); > > @@ -1274,9 +1353,32 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) > > cdns_i3c_master_enable(master); > > + if (m->secondary) { > + i3c_bus_maintenance_lock(&master->base.bus); > + cdns_i3c_master_update_devs(&master->base); > + i3c_bus_maintenance_unlock(&master->base.bus); > + } Okay, I changed my mind on this solution (it's not the first time that happens, and unfortunately won't be the last time either :-)). I think I don't like the idea of exposing the i3c_bus_maintenance_unlock/lock() functions in the end. I'd like to reconsider what you initially proposed: having an ->update_devs() hook that is called by the core, except I'd call it ->populate_bus(). BTW, there's still something that's unclear to me. You seem to populate the bus here and also when acquiring bus ownership. Is this correct? I'd expect it to be 'partially' populated at bus-init+defslvs time, which would trigger a mastership request if I3C devices are present (as we need to send a GETPID to know more about I3C devs). Also, what happens if i3c_master_add_i3c_dev_locked() fails? You don't seem to handle that case at all. > + > return 0; > } > > +static > +struct i3c_dev_desc *cdns_i3c_get_ibi_device(struct cdns_i3c_master *master, > + u32 ibir) > +{ > + struct i3c_dev_desc *dev; > + u32 id = IBIR_SLVID(ibir); > + > + if (id >= master->ibi.num_slots || (ibir & IBIR_ERROR)) > + return NULL; > + > + dev = master->ibi.slots[id]; > + if (!dev) > + return NULL; > + > + return dev; > +} > + > static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master, > u32 ibir) > { > @@ -1354,27 +1456,100 @@ static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master) > > case IBIR_TYPE_MR: > WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR)); > + master->mastership.ibir = ibir; > + master->mastership.mr_type = HANDOFF; > + queue_work(master->base.wq, > + &master->mastership.work); > + break; > default: > break; > } > } > } > > +static void cdns_i3c_master_bus_handoff(struct cdns_i3c_master *master) > +{ > + struct i3c_dev_desc *dev; > + > + dev = cdns_i3c_get_ibi_device(master, master->mastership.ibir); > + > + writel(MST_INT_MR_DONE, master->regs + MST_ICR); > + > + master->base.bus.cur_master = dev; > +} > + > +static void cdns_i3c_master_mastership_takeover(struct cdns_i3c_master *master) > +{ > + if (master->base.init_done) { Can this really happen that init_done is not set when you reach this point. > + i3c_bus_maintenance_lock(&master->base.bus); > + cdns_i3c_master_update_devs(&master->base); > + i3c_bus_maintenance_unlock(&master->base.bus); > + > + i3c_master_register_new_devs(&master->base); The core will somehow be informed that this master now owns the bus, so it can call i3c_master_register_new_devs() for us, right? But as said above, I'm not even sure this is correct to do it from here. I'd expect this to happen at DEFSLVS or BUS init time. > + } > + > + writel(readl(master->regs + CTRL) & ~CTRL_MST_ACK, master->regs + CTRL); > +} > + > +static void cdns_i3c_sec_master_event_up(struct cdns_i3c_master *master) Again, not specific to secondary masters, the primary master can go through that path too. > +{ > + u32 status; > + > + writel(SLV_INT_EVENT_UP, master->regs + SLV_ICR); > + status = readl(master->regs + SLV_STATUS1); > + if (!(status & SLV_STATUS1_MR_DIS) && > + !master->base.this) { > + master->mastership.mr_type = REQUEST; > + queue_work(master->wq, &master->mastership.work); > + } > +}
Hi Boris, I'm sorry for my late response. I hope you remember this thread :-) I'm implementing this and have some questions. The 03/30/2019 16:44, Boris Brezillon wrote: > > > > @@ -1274,9 +1353,32 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) > > > > cdns_i3c_master_enable(master); > > > > + if (m->secondary) { > > + i3c_bus_maintenance_lock(&master->base.bus); > > + cdns_i3c_master_update_devs(&master->base); > > + i3c_bus_maintenance_unlock(&master->base.bus); > > + } > > Okay, I changed my mind on this solution (it's not the first time that > happens, and unfortunately won't be the last time either :-)). I think > I don't like the idea of exposing the i3c_bus_maintenance_unlock/lock() > functions in the end. Ok :-) > > I'd like to reconsider what you initially proposed: having an > ->update_devs() hook that is called by the core, except I'd call it > ->populate_bus(). Ok, we can back to previous approach. > > BTW, there's still something that's unclear to me. You seem to populate > the bus here and also when acquiring bus ownership. Is this correct? Yes, this is correct. I'm doing this here to register all the devices received by DEFSLVS on master initialization time. I'm also populating new devices when acquiring the bus because some device could join the bus dynamically and we want to register this new devices on our side also. > I'd expect it to be 'partially' populated at bus-init+defslvs time, > which would trigger a mastership request if I3C devices are present (as > we need to send a GETPID to know more about I3C devs). So, you want to allocate and attach devices and then, when possible get devices info and register them? I mean when mastership request is possible. If not, just leave devices allocated and register them when ENEC(MR) received, correct? Previously, I allocated and registered all the devices after successful mastership request. Which way is better in your opinion? > > Also, what happens if i3c_master_add_i3c_dev_locked() fails? You > don't seem to handle that case at all. For now, I just skipped it silently. > > > + > > +static void cdns_i3c_master_mastership_takeover(struct cdns_i3c_master *master) > > +{ > > + if (master->base.init_done) { > > Can this really happen that init_done is not set when you reach this > point. Yes, it was possible. Mastership was taken but master wasn't registered yet. With new approach I think this won't happen. > > > + i3c_bus_maintenance_lock(&master->base.bus); > > + cdns_i3c_master_update_devs(&master->base); > > + i3c_bus_maintenance_unlock(&master->base.bus); > > + > > + i3c_master_register_new_devs(&master->base); > > The core will somehow be informed that this master now owns the bus, so > it can call i3c_master_register_new_devs() for us, right? I think it can. I'm sure it worked like that before. When HC driver changed cur_master, new devices were populated. > > But as said above, I'm not even sure this is correct to do it from > here. I'd expect this to happen at DEFSLVS or BUS init time. > Ok. New(Previous) approach allows that.
On Mon, 29 Apr 2019 11:36:42 +0100 Przemyslaw Gaj <pgaj@cadence.com> wrote: > Hi Boris, > > I'm sorry for my late response. I hope you remember this thread :-) Unfortunately not :-/, and it's now my turn to apologize for the late reply. > I'm implementing this and have some questions. > > The 03/30/2019 16:44, Boris Brezillon wrote: > > > > > > @@ -1274,9 +1353,32 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) > > > > > > cdns_i3c_master_enable(master); > > > > > > + if (m->secondary) { > > > + i3c_bus_maintenance_lock(&master->base.bus); > > > + cdns_i3c_master_update_devs(&master->base); > > > + i3c_bus_maintenance_unlock(&master->base.bus); > > > + } > > > > Okay, I changed my mind on this solution (it's not the first time that > > happens, and unfortunately won't be the last time either :-)). I think > > I don't like the idea of exposing the i3c_bus_maintenance_unlock/lock() > > functions in the end. > > Ok :-) > > > > > I'd like to reconsider what you initially proposed: having an > > ->update_devs() hook that is called by the core, except I'd call it > > ->populate_bus(). > > Ok, we can back to previous approach. > > > > > BTW, there's still something that's unclear to me. You seem to populate > > the bus here and also when acquiring bus ownership. Is this correct? > > Yes, this is correct. I'm doing this here to register all the devices received > by DEFSLVS on master initialization time. I'm also populating new devices when > acquiring the bus because some device could join the bus dynamically and we > want to register this new devices on our side also. Hm, I don't get that part. I thought we were supposed to add devices as soon as we know about them. In case of HJ and assuming your master is not currently owning the bus, the active master should send you a DEFSLVS which should serve as a trigger for registering new devs on all non active masters. Since registering new devices will trigger a mastership handover to query devs info (PID + other stuff) we should be all good, right? > > > I'd expect it to be 'partially' populated at bus-init+defslvs time, > > which would trigger a mastership request if I3C devices are present (as > > we need to send a GETPID to know more about I3C devs). > > So, you want to allocate and attach devices and then, when possible get devices > info and register them? I mean when mastership request is possible. If not, > just leave devices allocated and register them when ENEC(MR) received, correct? Kind of, yes. We can probably just have a "want_to_acquire_bus" flag set, and the partially registered/discovered devices present in the master list would be registered automatically every time the master acquires bus ownership. This way we can re-use this logic for any operation that requires the master to own the bus to do something specific. > > Previously, I allocated and registered all the devices after successful > mastership request. Which way is better in your opinion? That's a solution too, but it feels like a lot of generic code is open-coded in the driver if we do it this way. I know I'm the one who suggested this approach, but now that I see the code, I realize I was wrong (sorry about that). > > > > > Also, what happens if i3c_master_add_i3c_dev_locked() fails? You > > don't seem to handle that case at all. > > For now, I just skipped it silently. We should at least print an error/warning. > > > > > > + > > > +static void cdns_i3c_master_mastership_takeover(struct cdns_i3c_master *master) > > > +{ > > > + if (master->base.init_done) { > > > > Can this really happen that init_done is not set when you reach this > > point. > > Yes, it was possible. Mastership was taken but master wasn't registered yet. > With new approach I think this won't happen. One more reason to switch to the new approach. > > > > > > + i3c_bus_maintenance_lock(&master->base.bus); > > > + cdns_i3c_master_update_devs(&master->base); > > > + i3c_bus_maintenance_unlock(&master->base.bus); > > > + > > > + i3c_master_register_new_devs(&master->base); > > > > The core will somehow be informed that this master now owns the bus, so > > it can call i3c_master_register_new_devs() for us, right? > > I think it can. I'm sure it worked like that before. When HC driver changed > cur_master, new devices were populated. > > > > > But as said above, I'm not even sure this is correct to do it from > > here. I'd expect this to happen at DEFSLVS or BUS init time. > > > > Ok. New(Previous) approach allows that. > Ok, good.
diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c index 237f24a..61d6416 100644 --- a/drivers/i3c/master/i3c-master-cdns.c +++ b/drivers/i3c/master/i3c-master-cdns.c @@ -157,6 +157,7 @@ #define SLV_IMR 0x48 #define SLV_ICR 0x4c #define SLV_ISR 0x50 +#define SLV_INT_DEFSLVS BIT(21) #define SLV_INT_TM BIT(20) #define SLV_INT_ERROR BIT(19) #define SLV_INT_EVENT_UP BIT(18) @@ -388,8 +389,19 @@ struct cdns_i3c_xfer { struct cdns_i3c_cmd cmds[0]; }; +enum cdns_i3c_mr { + REQUEST, + HANDOFF, + TAKEOVER +}; + struct cdns_i3c_master { struct work_struct hj_work; + struct { + struct work_struct work; + enum cdns_i3c_mr mr_type; + u32 ibir; + } mastership; struct i3c_master_controller base; u32 free_rr_slots; unsigned int maxdevs; @@ -408,6 +420,8 @@ struct cdns_i3c_master { struct clk *pclk; struct cdns_i3c_master_caps caps; unsigned long i3c_scl_lim; + struct device *parent; + struct workqueue_struct *wq; }; static inline struct cdns_i3c_master * @@ -663,6 +677,88 @@ static void cdns_i3c_master_unqueue_xfer(struct cdns_i3c_master *master, spin_unlock_irqrestore(&master->xferqueue.lock, flags); } +static void +cdns_i3c_master_i3c_dev_rr_to_info(struct cdns_i3c_master *master, + unsigned int slot, + struct i3c_device_info *info) +{ + u32 rr; + + memset(info, 0, sizeof(*info)); + rr = readl(master->regs + DEV_ID_RR0(slot)); + info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr); + rr = readl(master->regs + DEV_ID_RR2(slot)); + info->dcr = rr; + info->bcr = rr >> 8; + info->pid = rr >> 16; + info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16; +} + +static void +cdns_i3c_master_i2c_dev_rr_to_info(struct cdns_i3c_master *master, + unsigned int slot, + u16 *addr, u8 *lvr) +{ + u32 rr; + + rr = readl(master->regs + DEV_ID_RR0(slot)); + *addr = DEV_ID_RR0_GET_DEV_ADDR(rr); + rr = readl(master->regs + DEV_ID_RR2(slot)); + *lvr = rr; +} + +static +int cdns_i3c_sec_master_request_mastership(struct i3c_master_controller *m) +{ + struct cdns_i3c_master *master = to_cdns_i3c_master(m); + u32 status; + int ret; + + status = readl(master->regs + MST_STATUS0); + if (WARN_ON(status & MST_STATUS0_MASTER_MODE)) + return -EEXIST; + + status = readl(master->regs + SLV_STATUS1); + if (status & SLV_STATUS1_MR_DIS) + return -EACCES; + + writel(SLV_INT_MR_DONE, master->regs + SLV_IER); + writel(readl(master->regs + CTRL) | CTRL_MST_INIT | CTRL_MST_ACK, + master->regs + CTRL); + + ret = readl_poll_timeout(master->regs + MST_STATUS0, status, + status & MST_STATUS0_MASTER_MODE, 100, + 100000); + return ret; +} + +static void cdns_i3c_master_update_devs(struct i3c_master_controller *m) +{ + struct cdns_i3c_master *master = to_cdns_i3c_master(m); + u32 val, newdevs; + u16 addr; + u8 lvr; + int slot; + struct i3c_device_info i3c_info; + + newdevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK; + for (slot = 1; slot <= master->maxdevs; slot++) { + val = readl(master->regs + DEV_ID_RR0(slot)); + + if ((newdevs & BIT(slot)) && (val & DEV_ID_RR0_IS_I3C)) { + cdns_i3c_master_i3c_dev_rr_to_info(master, slot, + &i3c_info); + + i3c_master_add_i3c_dev_locked(m, i3c_info.dyn_addr); + } else if ((newdevs & BIT(slot)) && + !(val & DEV_ID_RR0_IS_I3C)) { + cdns_i3c_master_i2c_dev_rr_to_info(master, slot, + &addr, &lvr); + i3c_master_add_i2c_dev(m, addr, lvr); + } + } +} + static enum i3c_error_code cdns_i3c_cmd_get_err(struct cdns_i3c_cmd *cmd) { switch (cmd->error) { @@ -913,6 +1009,7 @@ static int cdns_i3c_master_get_rr_slot(struct cdns_i3c_master *master, return ffs(master->free_rr_slots) - 1; } + activedevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK; @@ -1005,9 +1102,9 @@ static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) master->free_rr_slots &= ~BIT(slot); i2c_dev_set_master_data(dev, data); - writel(prepare_rr0_dev_address(dev->boardinfo->base.addr), + writel(prepare_rr0_dev_address(dev->addr), master->regs + DEV_ID_RR0(data->id)); - writel(dev->boardinfo->lvr, master->regs + DEV_ID_RR2(data->id)); + writel(dev->lvr, master->regs + DEV_ID_RR2(data->id)); writel(readl(master->regs + DEVS_CTRL) | DEVS_CTRL_DEV_ACTIVE(data->id), master->regs + DEVS_CTRL); @@ -1037,22 +1134,6 @@ static void cdns_i3c_master_bus_cleanup(struct i3c_master_controller *m) cdns_i3c_master_disable(master); } -static void cdns_i3c_master_dev_rr_to_info(struct cdns_i3c_master *master, - unsigned int slot, - struct i3c_device_info *info) -{ - u32 rr; - - memset(info, 0, sizeof(*info)); - rr = readl(master->regs + DEV_ID_RR0(slot)); - info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr); - rr = readl(master->regs + DEV_ID_RR2(slot)); - info->dcr = rr; - info->bcr = rr >> 8; - info->pid = rr >> 16; - info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16; -} - static void cdns_i3c_master_upd_i3c_scl_lim(struct cdns_i3c_master *master) { struct i3c_master_controller *m = &master->base; @@ -1180,10 +1261,6 @@ static int cdns_i3c_master_do_daa(struct i3c_master_controller *m) cdns_i3c_master_upd_i3c_scl_lim(master); - /* Unmask Hot-Join and Mastership request interrupts. */ - i3c_master_enec_locked(m, I3C_BROADCAST_ADDR, - I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR); - return 0; } @@ -1247,15 +1324,17 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) prescl1 = PRESCL_CTRL1_OD_LOW(ncycles); writel(prescl1, master->regs + PRESCL_CTRL1); - /* Get an address for the master. */ - ret = i3c_master_get_free_addr(m, 0); - if (ret < 0) - return ret; + if (!m->secondary) { + /* Get an address for the master. */ + ret = i3c_master_get_free_addr(m, 0); + if (ret < 0) + return ret; - writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C, - master->regs + DEV_ID_RR0(0)); + writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C, + master->regs + DEV_ID_RR0(0)); + } - cdns_i3c_master_dev_rr_to_info(master, 0, &info); + cdns_i3c_master_i3c_dev_rr_to_info(master, 0, &info); if (info.bcr & I3C_BCR_HDR_CAP) info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR); @@ -1274,9 +1353,32 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) cdns_i3c_master_enable(master); + if (m->secondary) { + i3c_bus_maintenance_lock(&master->base.bus); + cdns_i3c_master_update_devs(&master->base); + i3c_bus_maintenance_unlock(&master->base.bus); + } + return 0; } +static +struct i3c_dev_desc *cdns_i3c_get_ibi_device(struct cdns_i3c_master *master, + u32 ibir) +{ + struct i3c_dev_desc *dev; + u32 id = IBIR_SLVID(ibir); + + if (id >= master->ibi.num_slots || (ibir & IBIR_ERROR)) + return NULL; + + dev = master->ibi.slots[id]; + if (!dev) + return NULL; + + return dev; +} + static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master, u32 ibir) { @@ -1354,27 +1456,100 @@ static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master) case IBIR_TYPE_MR: WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR)); + master->mastership.ibir = ibir; + master->mastership.mr_type = HANDOFF; + queue_work(master->base.wq, + &master->mastership.work); + break; default: break; } } } +static void cdns_i3c_master_bus_handoff(struct cdns_i3c_master *master) +{ + struct i3c_dev_desc *dev; + + dev = cdns_i3c_get_ibi_device(master, master->mastership.ibir); + + writel(MST_INT_MR_DONE, master->regs + MST_ICR); + + master->base.bus.cur_master = dev; +} + +static void cdns_i3c_master_mastership_takeover(struct cdns_i3c_master *master) +{ + if (master->base.init_done) { + i3c_bus_maintenance_lock(&master->base.bus); + cdns_i3c_master_update_devs(&master->base); + i3c_bus_maintenance_unlock(&master->base.bus); + + i3c_master_register_new_devs(&master->base); + } + + writel(readl(master->regs + CTRL) & ~CTRL_MST_ACK, master->regs + CTRL); +} + +static void cdns_i3c_sec_master_event_up(struct cdns_i3c_master *master) +{ + u32 status; + + writel(SLV_INT_EVENT_UP, master->regs + SLV_ICR); + status = readl(master->regs + SLV_STATUS1); + if (!(status & SLV_STATUS1_MR_DIS) && + !master->base.this) { + master->mastership.mr_type = REQUEST; + queue_work(master->wq, &master->mastership.work); + } +} + +static void cdns_i3c_sec_mastership_done(struct cdns_i3c_master *master) +{ + writel(SLV_INT_MR_DONE, master->regs + SLV_ICR); + + master->base.bus.cur_master = master->base.this; + + if (master->base.this) { + master->mastership.mr_type = TAKEOVER; + queue_work(master->base.wq, &master->mastership.work); + } +} + static irqreturn_t cdns_i3c_master_interrupt(int irq, void *data) { struct cdns_i3c_master *master = data; u32 status; - status = readl(master->regs + MST_ISR); - if (!(status & readl(master->regs + MST_IMR))) - return IRQ_NONE; + status = readl(master->regs + MST_STATUS0); + + if (!master->base.this || + master->base.this != master->base.bus.cur_master) { + status = readl(master->regs + SLV_ISR); + + if (!(status & readl(master->regs + SLV_IMR))) + return IRQ_NONE; + + if (status & SLV_INT_MR_DONE) + cdns_i3c_sec_mastership_done(master); - spin_lock(&master->xferqueue.lock); - cdns_i3c_master_end_xfer_locked(master, status); - spin_unlock(&master->xferqueue.lock); + if (status & SLV_INT_EVENT_UP) + cdns_i3c_sec_master_event_up(master); + } else { + status = readl(master->regs + MST_ISR); + if (!(status & readl(master->regs + MST_IMR))) + return IRQ_NONE; + + spin_lock(&master->xferqueue.lock); + cdns_i3c_master_end_xfer_locked(master, status); + spin_unlock(&master->xferqueue.lock); - if (status & MST_INT_IBIR_THR) - cnds_i3c_master_demux_ibis(master); + if (status & MST_INT_IBIR_THR) + cnds_i3c_master_demux_ibis(master); + + if (status & MST_INT_MR_DONE) + cdns_i3c_master_bus_handoff(master); + } return IRQ_HANDLED; } @@ -1443,30 +1618,54 @@ static int cdns_i3c_master_enable_ibi(struct i3c_dev_desc *dev) return ret; } -static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev, - const struct i3c_ibi_setup *req) +static int cdns_i3c_master_find_ibi_slot(struct cdns_i3c_master *master, + struct i3c_dev_desc *dev, + s16 *slot) { - struct i3c_master_controller *m = i3c_dev_get_master(dev); - struct cdns_i3c_master *master = to_cdns_i3c_master(m); - struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); unsigned long flags; unsigned int i; - - data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); - if (IS_ERR(data->ibi_pool)) - return PTR_ERR(data->ibi_pool); + int ret = -ENOENT; spin_lock_irqsave(&master->ibi.lock, flags); for (i = 0; i < master->ibi.num_slots; i++) { - if (!master->ibi.slots[i]) { - data->ibi = i; - master->ibi.slots[i] = dev; + /* + * We only need 'SIR' slots to describe IBI-capable devices. + * This slot may be used by mastership request interrupt, + * We can ruse the same 'SIR' map entry. + */ + if (master->ibi.slots[i] == dev) { + *slot = i; + ret = 0; break; } } + + if (ret) + for (i = 0; i < master->ibi.num_slots; i++) { + if (!master->ibi.slots[i]) { + master->ibi.slots[i] = dev; + *slot = i; + ret = 0; + break; + } + } spin_unlock_irqrestore(&master->ibi.lock, flags); - if (i < master->ibi.num_slots) + return ret; +} + +static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev, + const struct i3c_ibi_setup *req) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct cdns_i3c_master *master = to_cdns_i3c_master(m); + struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + + data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); + if (IS_ERR(data->ibi_pool)) + return PTR_ERR(data->ibi_pool); + + if (cdns_i3c_master_find_ibi_slot(master, dev, &data->ibi) == 0) return 0; i3c_generic_ibi_free_pool(data->ibi_pool); @@ -1475,6 +1674,51 @@ static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev, return -ENOSPC; } +static int +cdns_i3c_master_enable_mastership_events(struct i3c_master_controller *m) +{ + struct cdns_i3c_master *master = to_cdns_i3c_master(m); + struct cdns_i3c_i2c_dev_data *data; + struct i3c_dev_desc *i3cdev; + unsigned long flags; + u32 sircfg, sirmap; + int ret; + + i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { + if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) != I3C_BCR_I3C_MASTER) + continue; + + data = i3c_dev_get_master_data(i3cdev); + if (!data) + continue; + + ret = cdns_i3c_master_find_ibi_slot(master, i3cdev, &data->ibi); + if (ret) + continue; + + spin_lock_irqsave(&master->ibi.lock, flags); + sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi)); + sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi); + sircfg = SIR_MAP_DEV_ROLE(i3cdev->info.bcr >> 6) | + SIR_MAP_DEV_DA(i3cdev->info.dyn_addr) | + SIR_MAP_DEV_PL(i3cdev->info.max_ibi_len) | + SIR_MAP_DEV_ACK; + + if (i3cdev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) + sircfg |= SIR_MAP_DEV_SLOW; + + sirmap |= SIR_MAP_DEV_CONF(data->ibi, sircfg); + writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi)); + spin_unlock_irqrestore(&master->ibi.lock, flags); + } + + /* Unmask Hot-Join and Mastership request interrupts. */ + i3c_master_enec_locked(&master->base, I3C_BROADCAST_ADDR, + I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR); + + return 0; +} + static void cdns_i3c_master_free_ibi(struct i3c_dev_desc *dev) { struct i3c_master_controller *m = i3c_dev_get_master(dev); @@ -1490,6 +1734,52 @@ static void cdns_i3c_master_free_ibi(struct i3c_dev_desc *dev) i3c_generic_ibi_free_pool(data->ibi_pool); } +static int +cdns_i3c_master_disable_mastership_events(struct i3c_master_controller *m) +{ + struct cdns_i3c_master *master = to_cdns_i3c_master(m); + struct cdns_i3c_i2c_dev_data *data; + struct i3c_dev_desc *i3cdev; + unsigned long flags; + u32 sirmap; + int ret; + + ret = i3c_master_disec_locked(m, I3C_BROADCAST_ADDR, + I3C_CCC_EVENT_MR); + if (ret) + return ret; + + i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { + if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) != I3C_BCR_I3C_MASTER) + continue; + + data = i3c_dev_get_master_data(i3cdev); + + ret = cdns_i3c_master_find_ibi_slot(master, i3cdev, &data->ibi); + if (ret) + continue; + + /* + * Do not modify SIR register and cleanup slots + * if regular IBI is enabled for this device. + */ + if (master->ibi.slots[data->ibi]->ibi->handler) + continue; + + spin_lock_irqsave(&master->ibi.lock, flags); + sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi)); + sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi); + sirmap |= SIR_MAP_DEV_CONF(data->ibi, + SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR)); + writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi)); + spin_unlock_irqrestore(&master->ibi.lock, flags); + + cdns_i3c_master_free_ibi(i3cdev); + } + + return ret; +} + static void cdns_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot) { @@ -1516,6 +1806,9 @@ static const struct i3c_master_controller_ops cdns_i3c_master_ops = { .request_ibi = cdns_i3c_master_request_ibi, .free_ibi = cdns_i3c_master_free_ibi, .recycle_ibi_slot = cdns_i3c_master_recycle_ibi_slot, + .request_mastership = cdns_i3c_sec_master_request_mastership, + .enable_mr_events = cdns_i3c_master_enable_mastership_events, + .disable_mr_events = cdns_i3c_master_disable_mastership_events }; static void cdns_i3c_master_hj(struct work_struct *work) @@ -1527,10 +1820,80 @@ static void cdns_i3c_master_hj(struct work_struct *work) i3c_master_do_daa(&master->base); } +static int cdns_i3c_sec_master_bus_init(struct cdns_i3c_master *master) +{ + u32 val; + int ret; + + val = readl(master->regs + SLV_STATUS1); + + if (!(val & SLV_STATUS1_HAS_DA)) + return -EFAULT; + + i3c_bus_maintenance_lock(&master->base.bus); + ret = cdns_i3c_sec_master_request_mastership(&master->base); + i3c_bus_maintenance_unlock(&master->base.bus); + + return ret; +} + +static void +cdns_i3c_master_mastership_request(struct cdns_i3c_master *master) +{ + int ret; + + ret = cdns_i3c_sec_master_bus_init(master); + if (ret) + return; + + ret = i3c_master_register(&master->base, master->parent, + &cdns_i3c_master_ops, true); + if (ret) + dev_err(&master->base.dev, "Master register failed\n"); +} + +static void cdns_i3c_master_mastership_handoff(struct cdns_i3c_master *master) +{ + int ret; + + struct i3c_dev_desc *dev; + u32 ibir = master->mastership.ibir; + + dev = cdns_i3c_get_ibi_device(master, ibir); + if (!dev) + return; + + ret = i3c_master_mastership_ack(&master->base, dev->info.dyn_addr); + if (ret) + dev_err(&master->base.dev, "Mastership handoff failed\n"); +} + +static void cdns_i3c_master_mastership(struct work_struct *work) +{ + struct cdns_i3c_master *master = container_of(work, + struct cdns_i3c_master, + mastership.work); + + switch (master->mastership.mr_type) { + case REQUEST: + cdns_i3c_master_mastership_request(master); + break; + case HANDOFF: + cdns_i3c_master_mastership_handoff(master); + break; + case TAKEOVER: + cdns_i3c_master_mastership_takeover(master); + break; + default: + break; + } +} + static int cdns_i3c_master_probe(struct platform_device *pdev) { struct cdns_i3c_master *master; struct resource *res; + bool secondary = false; int ret, irq; u32 val; @@ -1572,6 +1935,9 @@ static int cdns_i3c_master_probe(struct platform_device *pdev) INIT_LIST_HEAD(&master->xferqueue.list); INIT_WORK(&master->hj_work, cdns_i3c_master_hj); + INIT_WORK(&master->mastership.work, + cdns_i3c_master_mastership); + writel(0xffffffff, master->regs + MST_IDR); writel(0xffffffff, master->regs + SLV_IDR); ret = devm_request_irq(&pdev->dev, irq, cdns_i3c_master_interrupt, 0, @@ -1581,6 +1947,10 @@ static int cdns_i3c_master_probe(struct platform_device *pdev) platform_set_drvdata(pdev, master); + val = readl(master->regs + MST_STATUS0); + if (!(val & MST_STATUS0_MASTER_MODE)) + secondary = true; + val = readl(master->regs + CONF_STATUS0); /* Device ID0 is reserved to describe this master. */ @@ -1596,6 +1966,7 @@ static int cdns_i3c_master_probe(struct platform_device *pdev) spin_lock_init(&master->ibi.lock); master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val); + master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, sizeof(*master->ibi.slots), GFP_KERNEL); @@ -1604,15 +1975,31 @@ static int cdns_i3c_master_probe(struct platform_device *pdev) writel(IBIR_THR(1), master->regs + CMD_IBI_THR_CTRL); writel(MST_INT_IBIR_THR, master->regs + MST_IER); - writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL); + + if (secondary) { + ret = cdns_i3c_sec_master_bus_init(master); + if (ret) + goto err_postpone_init; + } else + writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL); ret = i3c_master_register(&master->base, &pdev->dev, - &cdns_i3c_master_ops, false); + &cdns_i3c_master_ops, secondary); if (ret) goto err_disable_sysclk; return 0; +err_postpone_init: + master->wq = alloc_workqueue("%s", 0, 0, pdev->name); + if (!master->wq) + return -ENOMEM; + + master->parent = &pdev->dev; + writel(SLV_INT_EVENT_UP, master->regs + SLV_IER); + + return 0; + err_disable_sysclk: clk_disable_unprepare(master->sysclk); @@ -1627,6 +2014,9 @@ static int cdns_i3c_master_remove(struct platform_device *pdev) struct cdns_i3c_master *master = platform_get_drvdata(pdev); int ret; + if (master->wq) + destroy_workqueue(master->wq); + ret = i3c_master_unregister(&master->base); if (ret) return ret; @@ -1653,6 +2043,7 @@ static struct platform_driver cdns_i3c_master = { module_platform_driver(cdns_i3c_master); MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>"); +MODULE_AUTHOR("Przemyslaw Gaj <pgaj@cadence.com>"); MODULE_DESCRIPTION("Cadence I3C master driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:cdns-i3c-master");
This patch adds support for mastership request to Cadence I3C master driver. Mastership is requested automatically after secondary master receives mastership ENEC event. This allows secondary masters to initialize their bus. Signed-off-by: Przemyslaw Gaj <pgaj@cadence.com> --- Main changes between v3 and v4: - Refactored the code Main changes between v2 and v3: - Add mastership type - Add postponed master registration - Add update device definition on bus initialization time - Removed redundant mastership work structs - Reworked IBI slot lookup - Reworked Mastership event enabling/disabling Changes in v2: - Add work structs for mastership purpose - Add missing mastership disable feature --- drivers/i3c/master/i3c-master-cdns.c | 495 +++++++++++++++++++++++++++++++---- 1 file changed, 443 insertions(+), 52 deletions(-)