Message ID | 20210715082413.3042149-2-xiaoning.wang@nxp.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show
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dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB5623.eurprd04.prod.outlook.com (2603:10a6:20b:a9::13) by AM6PR04MB4167.eurprd04.prod.outlook.com (2603:10a6:209:4e::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21; Thu, 15 Jul 2021 08:23:03 +0000 Received: from AM6PR04MB5623.eurprd04.prod.outlook.com ([fe80::74f8:10b:8efd:b265]) by AM6PR04MB5623.eurprd04.prod.outlook.com ([fe80::74f8:10b:8efd:b265%5]) with mapi id 15.20.4308.027; Thu, 15 Jul 2021 08:23:03 +0000 From: Clark Wang <xiaoning.wang@nxp.com> To: miquel.raynal@bootlin.com, conor.culhane@silvaco.com, alexandre.belloni@bootlin.com, vitor.soares@synopsys.com, boris.brezillon@bootlin.com Cc: linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, xiaoning.wang@nxp.com Subject: [PATCH 1/4] i3c: master: svc: move module reset behind clk enable Date: Thu, 15 Jul 2021 16:24:10 +0800 Message-Id: <20210715082413.3042149-2-xiaoning.wang@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715082413.3042149-1-xiaoning.wang@nxp.com> References: <20210715082413.3042149-1-xiaoning.wang@nxp.com> X-ClientProxiedBy: SG2PR03CA0142.apcprd03.prod.outlook.com (2603:1096:4:c8::15) To AM6PR04MB5623.eurprd04.prod.outlook.com (2603:10a6:20b:a9::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR03CA0142.apcprd03.prod.outlook.com (2603:1096:4:c8::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.9 via Frontend Transport; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-i3c" <linux-i3c-bounces@lists.infradead.org> Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org |
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i3c: master: svc: some bug fixes
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Hi Clark, Clark Wang <xiaoning.wang@nxp.com> wrote on Thu, 15 Jul 2021 16:24:10 +0800: > Reset I3C module will R/W its regs, so enable its clocks first. > > Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Thanks, Miquèl
diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c index 879e5a64acaf..c25a372f6820 100644 --- a/drivers/i3c/master/svc-i3c-master.c +++ b/drivers/i3c/master/svc-i3c-master.c @@ -1381,8 +1381,6 @@ static int svc_i3c_master_probe(struct platform_device *pdev) master->dev = dev; - svc_i3c_master_reset(master); - ret = clk_prepare_enable(master->pclk); if (ret) return ret; @@ -1419,6 +1417,8 @@ static int svc_i3c_master_probe(struct platform_device *pdev) platform_set_drvdata(pdev, master); + svc_i3c_master_reset(master); + /* Register the master */ ret = i3c_master_register(&master->base, &pdev->dev, &svc_i3c_master_ops, false);
Reset I3C module will R/W its regs, so enable its clocks first. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> --- drivers/i3c/master/svc-i3c-master.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)