| Message ID | 20230216151057.293764-1-zenghuchen@google.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v3] i3c: update dw-i3c-master i3c_clk_cfg function | expand |
On Thu, 16 Feb 2023 10:10:57 -0500, Jack Chen wrote: > Bus-speed could be default(12.5MHz) or defined by users in dts. > Dw-i3c-master should not hard-code the initial speed to be > I3C_BUS_TYP_I3C_SCL_RATE (12.5MHz) > And because of Synopsys's I3C controller limit (hcnt/lcnt register > length) and core-clk provided, there is a limit to bus speed, too. > For example, when core-clk is 250 MHz, the bus speed cannot be > lowered below 1MHz. > > [...] Applied, thanks! [1/1] i3c: update dw-i3c-master i3c_clk_cfg function commit: 07eac9c306a0efd73a43804b50c88c67696a3c74 Best regards,
diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c index 51a8608203de..48954d3e6571 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -531,7 +531,7 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *master) if (hcnt < SCL_I3C_TIMING_CNT_MIN) hcnt = SCL_I3C_TIMING_CNT_MIN; - lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_TYP_I3C_SCL_RATE) - hcnt; + lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt; if (lcnt < SCL_I3C_TIMING_CNT_MIN) lcnt = SCL_I3C_TIMING_CNT_MIN; @@ -541,7 +541,8 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *master) if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT)) writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); - lcnt = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period); + lcnt = max_t(u8, + DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt); scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
Bus-speed could be default(12.5MHz) or defined by users in dts. Dw-i3c-master should not hard-code the initial speed to be I3C_BUS_TYP_I3C_SCL_RATE (12.5MHz) And because of Synopsys's I3C controller limit (hcnt/lcnt register length) and core-clk provided, there is a limit to bus speed, too. For example, when core-clk is 250 MHz, the bus speed cannot be lowered below 1MHz. Tested: tested with an i3c sensor and captured with a logic analyzer. Signed-off-by: Jack Chen <zenghuchen@google.com> --- [v3] - change the target tree to be i3c/next [v2] - replace max with max_t drivers/i3c/master/dw-i3c-master.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)