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([10.237.72.152]) by fmsmga005.fm.intel.com with ESMTP; 20 Sep 2023 22:58:02 -0700 From: Jarkko Nikula To: Alexandre Belloni Cc: linux-i3c@lists.infradead.org, Jarkko Nikula Subject: [PATCH 07/12] i3c: mipi-i3c-hci: Fix race between bus cleanup and interrupt Date: Thu, 21 Sep 2023 08:56:59 +0300 Message-Id: <20230921055704.1087277-8-jarkko.nikula@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230921055704.1087277-1-jarkko.nikula@linux.intel.com> References: <20230921055704.1087277-1-jarkko.nikula@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_225810_204476_31847FBA X-CRM114-Status: GOOD ( 10.06 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org If there is a transfer error during i3c_master_bus_init() and code goes doing the bus cleanup in i3c_hci_bus_cleanup() there is possibility that i3c_hci_irq_handler() is running in parallel with hci->io->cleanup() which can be racy. Prevent this by waiting there is no pending interrupt on other CPU before doing the IO cleanup. This was observed with ring headers where first transfer failed and sometimes transfer error or ring transfer abort interrupt was coming simultaneously with the bus cleanup path. Signed-off-by: Jarkko Nikula --- drivers/i3c/master/mipi-i3c-hci/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index 76a3e6bb3665..d7fe8e62820a 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -161,10 +161,12 @@ static int i3c_hci_bus_init(struct i3c_master_controller *m) static void i3c_hci_bus_cleanup(struct i3c_master_controller *m) { struct i3c_hci *hci = to_i3c_hci(m); + struct platform_device *pdev = to_platform_device(m->dev.parent); DBG(""); reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE); + synchronize_irq(platform_get_irq(pdev, 0)); hci->io->cleanup(hci); if (hci->cmd == &mipi_i3c_hci_cmd_v1) mipi_i3c_hci_dat_v1.cleanup(hci);