| Message ID | 20250220061107.1718239-3-yschu@nuvoton.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for Nuvoton npcm845 i3c controller | expand |
On Thu, Feb 20, 2025 at 02:11:05PM +0800, Stanley Chu wrote: > From: Stanley Chu <yschu@nuvoton.com> > > Nuvoton npcm845 SoC uses the same Silvico IP but an older version. > Add npcm845 specific quirks. > > Signed-off-by: Stanley Chu <yschu@nuvoton.com> > --- > drivers/i3c/master/svc-i3c-master.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c > index d6057d8c7dec..c58440061d5a 100644 > --- a/drivers/i3c/master/svc-i3c-master.c > +++ b/drivers/i3c/master/svc-i3c-master.c > @@ -133,6 +133,22 @@ > #define SVC_I3C_EVENT_IBI GENMASK(7, 0) > #define SVC_I3C_EVENT_HOTJOIN BIT(31) > > +/* > + * SVC_I3C_QUIRK_FIFO_EMPTY: > + * I3C HW stalls the write transfer if the transmit FIFO becomes empty, > + * when new data is written to FIFO, I3C HW resumes the transfer but > + * the first transmitted data bit may have the wrong value. > + * Workaround: > + * Fill the FIFO in advance to prevent FIFO from becoming empty. > + */ > +#define SVC_I3C_QUIRK_FIFO_EMPTY BIT(0) > +/* > + * SVC_I3C_QUIRK_FLASE_SLVSTART: > + * I3C HW may generate an invalid SlvStart event when emitting a STOP. > + * If it is a true SlvStart, the MSTATUS state should be SLVREQ. > + */ > +#define SVC_I3C_QUIRK_FALSE_SLVSTART BIT(1) > + > struct svc_i3c_cmd { > u8 addr; > bool rnw; > @@ -216,6 +232,7 @@ struct svc_i3c_master { > struct mutex lock; > u32 enabled_events; > u32 mctrl_config; > + u32 quirks; struct svc_i3c_drvdata *drvdata; > }; > > /** > @@ -230,6 +247,14 @@ struct svc_i3c_i2c_dev_data { > struct i3c_generic_ibi_pool *ibi_pool; > }; > > +struct svc_i3c_drvdata { > + u32 quirks; > +}; > + > +const struct svc_i3c_drvdata npcm845_drvdata = { > + .quirks = SVC_I3C_QUIRK_FIFO_EMPTY | SVC_I3C_QUIRK_FALSE_SLVSTART, > +}; > + > static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask) > { > return !!(master->enabled_events & mask); > @@ -1811,6 +1836,7 @@ static int svc_i3c_master_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct svc_i3c_master *master; > + const struct svc_i3c_drvdata *data = of_device_get_match_data(dev); > int ret; > > master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); > @@ -1868,6 +1894,8 @@ static int svc_i3c_master_probe(struct platform_device *pdev) > } > > platform_set_drvdata(pdev, master); > + if (data) > + master->quirks = data->quirks; master->drvdata = of_device_get_match_data(dev); > > pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS); > pm_runtime_use_autosuspend(&pdev->dev); > @@ -1960,6 +1988,7 @@ static const struct dev_pm_ops svc_i3c_pm_ops = { > > static const struct of_device_id svc_i3c_master_of_match_tbl[] = { > { .compatible = "silvaco,i3c-master-v1"}, > + { .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata }, > { /* sentinel */ }, > }; > MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl); > -- > 2.34.1 >
diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c index d6057d8c7dec..c58440061d5a 100644 --- a/drivers/i3c/master/svc-i3c-master.c +++ b/drivers/i3c/master/svc-i3c-master.c @@ -133,6 +133,22 @@ #define SVC_I3C_EVENT_IBI GENMASK(7, 0) #define SVC_I3C_EVENT_HOTJOIN BIT(31) +/* + * SVC_I3C_QUIRK_FIFO_EMPTY: + * I3C HW stalls the write transfer if the transmit FIFO becomes empty, + * when new data is written to FIFO, I3C HW resumes the transfer but + * the first transmitted data bit may have the wrong value. + * Workaround: + * Fill the FIFO in advance to prevent FIFO from becoming empty. + */ +#define SVC_I3C_QUIRK_FIFO_EMPTY BIT(0) +/* + * SVC_I3C_QUIRK_FLASE_SLVSTART: + * I3C HW may generate an invalid SlvStart event when emitting a STOP. + * If it is a true SlvStart, the MSTATUS state should be SLVREQ. + */ +#define SVC_I3C_QUIRK_FALSE_SLVSTART BIT(1) + struct svc_i3c_cmd { u8 addr; bool rnw; @@ -216,6 +232,7 @@ struct svc_i3c_master { struct mutex lock; u32 enabled_events; u32 mctrl_config; + u32 quirks; }; /** @@ -230,6 +247,14 @@ struct svc_i3c_i2c_dev_data { struct i3c_generic_ibi_pool *ibi_pool; }; +struct svc_i3c_drvdata { + u32 quirks; +}; + +const struct svc_i3c_drvdata npcm845_drvdata = { + .quirks = SVC_I3C_QUIRK_FIFO_EMPTY | SVC_I3C_QUIRK_FALSE_SLVSTART, +}; + static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask) { return !!(master->enabled_events & mask); @@ -1811,6 +1836,7 @@ static int svc_i3c_master_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct svc_i3c_master *master; + const struct svc_i3c_drvdata *data = of_device_get_match_data(dev); int ret; master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); @@ -1868,6 +1894,8 @@ static int svc_i3c_master_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, master); + if (data) + master->quirks = data->quirks; pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS); pm_runtime_use_autosuspend(&pdev->dev); @@ -1960,6 +1988,7 @@ static const struct dev_pm_ops svc_i3c_pm_ops = { static const struct of_device_id svc_i3c_master_of_match_tbl[] = { { .compatible = "silvaco,i3c-master-v1"}, + { .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl);