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Tue, 28 Jan 2020 12:57:40 +0000 From: To: , , CC: , , , Subject: [PATCH v3 2/3] iio: adc: at91-sama5d2_adc: handle unfinished conversions Thread-Topic: [PATCH v3 2/3] iio: adc: at91-sama5d2_adc: handle unfinished conversions Thread-Index: AQHV1dqFbCPx79TfoEqT0jQK5BBdgw== Date: Tue, 28 Jan 2020 12:57:40 +0000 Message-ID: <1580216189-27418-3-git-send-email-eugen.hristev@microchip.com> References: <1580216189-27418-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1580216189-27418-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3784100a-ce25-4ba6-29ce-08d7a3f1a8b4 x-ms-traffictypediagnostic: DM5PR11MB1852: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 029651C7A1 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(376002)(366004)(39860400002)(136003)(396003)(346002)(199004)(189003)(6512007)(2616005)(107886003)(76116006)(54906003)(91956017)(110136005)(66446008)(64756008)(66556008)(66476007)(66946007)(316002)(8936002)(6486002)(186003)(5660300002)(71200400001)(81156014)(4326008)(2906002)(81166006)(478600001)(36756003)(86362001)(6506007)(8676002)(26005);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR11MB1852;H:DM5PR11MB1242.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: oWJjfWvDvCCQadEilKoPLCiwPNRK0XhxlfeUVX+A1xz0+vLDXypl9r4R/0DSvJ60GoT0DMaCZR/oW59KbqduexTw/0MtU6gqqsSt81dZttDB6Av2XE5YI/uifALJQSOwZadBr6iYkGEjBG+kBe3nHxRZ3xfEZbQYcVejteNWesUC9/khJN3rUA3VM4VScS1EFaAHQukBEtcA56EAIIsWbR31WQmEuXg8KEDwRD6s9lsDdRCOsJvSqmVbPsVCUDpG4j0ZZEE41SuBcKWNR6aXQaeyDjPiSRXdVRIbPexzgGhWzaqkVM7Cjl8ALjWCZsukSr61uepsWIU1XlLiiDzvzeUeOEstHBpMoBoo69w4zrodVgmytm30afrnsyRVOqCWds77NmZyRLtCHk342xYlXScVGG97dtDiuWfliSFamqotiGFO8fJ9FDn6BHpeuzqG x-ms-exchange-antispam-messagedata: wbZnnKHKulGMvYMxNKN51pEdnTyZGIloeSOoEnbgCuE2jQruFrxQSNsut1QhcxyVOjc8GX89PQ2x3gvHRI4Y2ubtC0A1lauSoqGd/WSnNFIK2WGQ31g7DLjwmYg1Fco8+2C0EoratAOSrVrKpZiRDg== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3784100a-ce25-4ba6-29ce-08d7a3f1a8b4 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jan 2020 12:57:40.4711 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Awa0eQYIg6q3o9KvpMUkoZkj0wFXFLPHJqHvqCUwg0crhCCBidfP+dJ11ZAT0Q30KK4wde/nxqesmkvk5iuUvPQl5TSJ9HkKNGVAn9p9Meg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1852 Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Eugen Hristev It can happen that on IRQ trigger, not all conversions are done if we are enabling multiple channels. The IRQ is triggered on first EOC (end of channel), but it can happen that not all channels are done. This leads into erroneous reports to userspace (zero values or previous values). To solve this, in trigger handler, check if the mask of done channels is the same as the mask of active scan channels. If it's the same, proceed and push to buffers. Otherwise, use usleep to sleep until the conversion is done or we timeout. Normally, it should happen that in a short time fashion, all channels are ready, since the first IRQ triggered. If a hardware fault happens (for example the clock suddently dissappears), the handler will not be completed, in which case we do not report anything to userspace anymore. Also, change from using the EOC interrupts to DRDY interrupt. This helps with the fact that not 'n' interrupt statuses are enabled, each being able to trigger an interrupt, and instead only data ready interrupt can wake up the CPU. Like this, when data is ready, check in handler which and how many channels are done. While the DRDY is raised, other IRQs cannot occur. Once the channel data is being read, we ack the IRQ and finish the conversion. Signed-off-by: Eugen Hristev --- Changes in v3: - rewrite some code as suggested by Jonathan (w.r.t. state and dma enabled in configure_trigger - move back enable_irq in reenable_trigger : looks like it was a leftover, thanks Jonathan Changes in v2: - move start of conversion to threaded irq, removed specific at91 pollfunc - add timeout to channel mask readiness check in trigger handler - use DRDY irq instead of EOC irqs. - move enable irq after DRDY has been acked in reenable_trigger drivers/iio/adc/at91-sama5d2_adc.c | 62 +++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 14 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 2a6950a..49c2b9d 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -100,6 +101,8 @@ #define AT91_SAMA5D2_IER_YRDY BIT(21) /* Interrupt Enable Register - TS pressure measurement ready */ #define AT91_SAMA5D2_IER_PRDY BIT(22) +/* Interrupt Enable Register - Data ready */ +#define AT91_SAMA5D2_IER_DRDY BIT(24) /* Interrupt Enable Register - general overrun error */ #define AT91_SAMA5D2_IER_GOVRE BIT(25) /* Interrupt Enable Register - Pen detect */ @@ -486,6 +489,21 @@ static inline int at91_adc_of_xlate(struct iio_dev *indio_dev, return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); } +static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) +{ + u32 mask = 0; + u8 bit; + + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->num_channels) { + struct iio_chan_spec const *chan = + at91_adc_chan_get(indio_dev, bit); + mask |= BIT(chan->channel); + } + + return mask & GENMASK(11, 0); +} + static void at91_adc_config_emr(struct at91_adc_state *st) { /* configure the extended mode register */ @@ -746,25 +764,23 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) at91_adc_writel(st, AT91_SAMA5D2_COR, cor); } - if (state) { + if (state) at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); - /* enable irq only if not using DMA */ - if (!st->dma_st.dma_chan) { - at91_adc_writel(st, AT91_SAMA5D2_IER, - BIT(chan->channel)); - } - } else { - /* disable irq only if not using DMA */ - if (!st->dma_st.dma_chan) { - at91_adc_writel(st, AT91_SAMA5D2_IDR, - BIT(chan->channel)); - } + else at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); - } } + /* Nothing to do if using DMA */ + if (st->dma_st.dma_chan) + return 0; + + if (state) + at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY); + else + at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY); + return 0; } @@ -781,6 +797,7 @@ static int at91_adc_reenable_trigger(struct iio_trigger *trig) /* Needed to ACK the DRDY interruption */ at91_adc_readl(st, AT91_SAMA5D2_LCDR); + return 0; } @@ -1015,6 +1032,22 @@ static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, int i = 0; int val; u8 bit; + u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); + unsigned int timeout = 50; + + /* + * Check if the conversion is ready. If not, wait a little bit, and + * in case of timeout exit with an error. + */ + while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask && + timeout) { + usleep_range(50, 100); + timeout--; + } + + /* Cannot read data, not ready. Continue without reporting data */ + if (!timeout) + return; for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->num_channels) { @@ -1281,7 +1314,8 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private) status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR); status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR); status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); - } else if (iio_buffer_enabled(indio) && !st->dma_st.dma_chan) { + } else if (iio_buffer_enabled(indio) && + (status & AT91_SAMA5D2_IER_DRDY)) { /* triggered buffer without DMA */ disable_irq_nosync(irq); iio_trigger_poll(indio->trig);