diff mbox

[16/16] arm: dts: sun8i: a83t: add thermal zone to A83T

Message ID 20180126151941.12183-17-embed3d@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Philipp Rossak Jan. 26, 2018, 3:19 p.m. UTC
This patch adds the thermal zones to the A83T. Sensor 0 is located in the
cpu cluster 0. Sensor 1 is located in cluster 1 and Sensor 3 is located
in the gpu.

Signed-off-by: Philipp Rossak <embed3d@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Samuel Holland Jan. 26, 2018, 4:25 p.m. UTC | #1
On 01/26/18 09:19, Philipp Rossak wrote:
> This patch adds the thermal zones to the A83T. Sensor 0 is located in the
> cpu cluster 0. Sensor 1 is located in cluster 1 and Sensor 3 is located
> in the gpu.

You mention sensor 3 here, but have sensor 2 in the device tree.

> Signed-off-by: Philipp Rossak <embed3d@gmail.com>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 9e53ff5ac4ed..4259a8726031 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -747,4 +747,24 @@
>  			#size-cells = <0>;
>  		};
>  	};
> +
> +	thermal-zones {
> +		cpu0_thermal: cpu0-thermal {
> +			polling-delay-passive = <1000>;
> +			polling-delay = <5000>;
> +			thermal-sensors = <&ths 0>;
> +		};
> +
> +		cpu1_thermal: cpu1-thermal {
> +			polling-delay-passive = <1000>;
> +			polling-delay = <5000>;
> +			thermal-sensors = <&ths 1>;
> +		};
> +
> +		gpu_thermal: gpu-thermal {
> +			polling-delay-passive = <1000>;
> +			polling-delay = <5000>;
> +			thermal-sensors = <&ths 2>;

                                           ^^^^ here

> +		};
> +	};
>  };
> 

Thanks,
Samuel
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Philipp Rossak Jan. 26, 2018, 5:35 p.m. UTC | #2
On 26.01.2018 17:25, Samuel Holland wrote:
> On 01/26/18 09:19, Philipp Rossak wrote:
>> This patch adds the thermal zones to the A83T. Sensor 0 is located in the
>> cpu cluster 0. Sensor 1 is located in cluster 1 and Sensor 3 is located
>> in the gpu.
> 
> You mention sensor 3 here, but have sensor 2 in the device tree.
That is a typo/wrong counting error. This should be sensor 2.

I will fix that in the next version of this patch series.

>> Signed-off-by: Philipp Rossak <embed3d@gmail.com>
>> ---
>>   arch/arm/boot/dts/sun8i-a83t.dtsi | 20 ++++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> index 9e53ff5ac4ed..4259a8726031 100644
>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> @@ -747,4 +747,24 @@
>>   			#size-cells = <0>;
>>   		};
>>   	};
>> +
>> +	thermal-zones {
>> +		cpu0_thermal: cpu0-thermal {
>> +			polling-delay-passive = <1000>;
>> +			polling-delay = <5000>;
>> +			thermal-sensors = <&ths 0>;
>> +		};
>> +
>> +		cpu1_thermal: cpu1-thermal {
>> +			polling-delay-passive = <1000>;
>> +			polling-delay = <5000>;
>> +			thermal-sensors = <&ths 1>;
>> +		};
>> +
>> +		gpu_thermal: gpu-thermal {
>> +			polling-delay-passive = <1000>;
>> +			polling-delay = <5000>;
>> +			thermal-sensors = <&ths 2>;
> 
>                                             ^^^^ here
> 
>> +		};
>> +	};
>>   };
>>
> 
> Thanks,
> Samuel
> 

Thanks,
Philipp
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diff mbox

Patch

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 9e53ff5ac4ed..4259a8726031 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -747,4 +747,24 @@ 
 			#size-cells = <0>;
 		};
 	};
+
+	thermal-zones {
+		cpu0_thermal: cpu0-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&ths 0>;
+		};
+
+		cpu1_thermal: cpu1-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&ths 1>;
+		};
+
+		gpu_thermal: gpu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+			thermal-sensors = <&ths 2>;
+		};
+	};
 };