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Wed, 19 Feb 2020 14:40:47 +0000 From: Jean-Baptiste Maneyrol To: jic23@kernel.org, linux-iio@vger.kernel.org Cc: Jean-Baptiste Maneyrol Subject: [PATCH v2 05/13] iio: imu: inv_mpu6050: early init of chip_config for use at setup Date: Wed, 19 Feb 2020 15:39:50 +0100 Message-Id: <20200219143958.3548-6-jmaneyrol@invensense.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200219143958.3548-1-jmaneyrol@invensense.com> References: <20200219143958.3548-1-jmaneyrol@invensense.com> X-ClientProxiedBy: BYAPR01CA0043.prod.exchangelabs.com (2603:10b6:a03:94::20) To CH2PR12MB4181.namprd12.prod.outlook.com (2603:10b6:610:a8::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from frgnb-12nlpn2.invcorp.invensense.com (77.157.193.39) by BYAPR01CA0043.prod.exchangelabs.com (2603:10b6:a03:94::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.17 via Frontend Transport; Wed, 19 Feb 2020 14:40:46 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [77.157.193.39] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b9eba5d1-c89d-46d3-f21f-08d7b549b517 X-MS-TrafficTypeDiagnostic: CH2PR12MB4213: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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More coherent, prevent possible mistakes. Signed-off-by: Jean-Baptiste Maneyrol --- drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | 15 +++++++-------- drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h | 1 - 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c index 0b06d6aa6469..85872e55154f 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c @@ -101,7 +101,7 @@ static const struct inv_mpu6050_reg_map reg_set_6050 = { static const struct inv_mpu6050_chip_config chip_config_6050 = { .fsr = INV_MPU6050_FSR_2000DPS, .lpf = INV_MPU6050_FILTER_20HZ, - .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(INV_MPU6050_INIT_FIFO_RATE), + .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50), .gyro_fifo_enable = false, .accl_fifo_enable = false, .temp_fifo_enable = false, @@ -370,20 +370,20 @@ static int inv_mpu6050_init_config(struct iio_dev *indio_dev) u8 d; struct inv_mpu6050_state *st = iio_priv(indio_dev); - result = inv_mpu6050_set_gyro_fsr(st, INV_MPU6050_FSR_2000DPS); + result = inv_mpu6050_set_gyro_fsr(st, st->chip_config.fsr); if (result) return result; - result = inv_mpu6050_set_lpf_regs(st, INV_MPU6050_FILTER_20HZ); + result = inv_mpu6050_set_lpf_regs(st, st->chip_config.lpf); if (result) return result; - d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(INV_MPU6050_INIT_FIFO_RATE); + d = st->chip_config.divider; result = regmap_write(st->map, st->reg->sample_rate_div, d); if (result) return result; - d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT); + d = (st->chip_config.accl_fs << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT); result = regmap_write(st->map, st->reg->accl_config, d); if (result) return result; @@ -392,9 +392,6 @@ static int inv_mpu6050_init_config(struct iio_dev *indio_dev) if (result) return result; - memcpy(&st->chip_config, hw_info[st->chip_type].config, - sizeof(struct inv_mpu6050_chip_config)); - /* * Internal chip period is 1ms (1kHz). * Let's use at the beginning the theorical value before measuring @@ -1116,6 +1113,8 @@ static int inv_check_and_setup_chip(struct inv_mpu6050_state *st) st->hw = &hw_info[st->chip_type]; st->reg = hw_info[st->chip_type].reg; + memcpy(&st->chip_config, hw_info[st->chip_type].config, + sizeof(st->chip_config)); /* check chip self-identification */ result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val); diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h index 9a81098a8b4d..d5edf903c076 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h @@ -321,7 +321,6 @@ struct inv_mpu6050_state { #define INV_MPU6050_TS_PERIOD_JITTER 4 /* init parameters */ -#define INV_MPU6050_INIT_FIFO_RATE 50 #define INV_MPU6050_MAX_FIFO_RATE 1000 #define INV_MPU6050_MIN_FIFO_RATE 4