diff mbox series

[v2,1/2] iio: adc: ti-ads8344: properly byte swap value

Message ID 20200416205428.437503-2-alexandre.belloni@bootlin.com
State New, archived
Headers show
Series iio: adc: ti-ads8344: driver improvements | expand

Commit Message

Alexandre Belloni April 16, 2020, 8:54 p.m. UTC
The first received byte is the MSB, followed by the LSB so the value needs
to be byte swapped.

Also, the ADC actually has a delay of one clock on the SPI bus. Read three
bytes to get the last bit.

Fixes: 8dd2d7c0fed7 ("iio: adc: Add driver for the TI ADS8344 A/DC chips")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 drivers/iio/adc/ti-ads8344.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Andy Shevchenko April 17, 2020, 10:44 a.m. UTC | #1
On Thu, Apr 16, 2020 at 11:55 PM Alexandre Belloni
<alexandre.belloni@bootlin.com> wrote:
>
> The first received byte is the MSB, followed by the LSB so the value needs
> to be byte swapped.
>
> Also, the ADC actually has a delay of one clock on the SPI bus. Read three
> bytes to get the last bit.
>

Can you show example of what is read and what is expected to be a correct value?
Because it seems I have been reported with similar issue on other TI
ADC chip [1]. Perhaps we have to fix all of them?

[1]: https://github.com/edison-fw/meta-intel-edison/issues/108

> Fixes: 8dd2d7c0fed7 ("iio: adc: Add driver for the TI ADS8344 A/DC chips")
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
>  drivers/iio/adc/ti-ads8344.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iio/adc/ti-ads8344.c b/drivers/iio/adc/ti-ads8344.c
> index 9a460807d46d..abe4b56c847c 100644
> --- a/drivers/iio/adc/ti-ads8344.c
> +++ b/drivers/iio/adc/ti-ads8344.c
> @@ -29,7 +29,7 @@ struct ads8344 {
>         struct mutex lock;
>
>         u8 tx_buf ____cacheline_aligned;
> -       u16 rx_buf;
> +       u8 rx_buf[3];
>  };
>
>  #define ADS8344_VOLTAGE_CHANNEL(chan, si)                              \
> @@ -89,11 +89,11 @@ static int ads8344_adc_conversion(struct ads8344 *adc, int channel,
>
>         udelay(9);
>
> -       ret = spi_read(spi, &adc->rx_buf, 2);
> +       ret = spi_read(spi, adc->rx_buf, sizeof(adc->rx_buf));
>         if (ret)
>                 return ret;
>
> -       return adc->rx_buf;
> +       return adc->rx_buf[0] << 9 | adc->rx_buf[1] << 1 | adc->rx_buf[2] >> 7;
>  }
>
>  static int ads8344_read_raw(struct iio_dev *iio,
> --
> 2.25.2
>
Andy Shevchenko April 17, 2020, 10:47 a.m. UTC | #2
On Fri, Apr 17, 2020 at 1:44 PM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
>
> On Thu, Apr 16, 2020 at 11:55 PM Alexandre Belloni
> <alexandre.belloni@bootlin.com> wrote:
> >
> > The first received byte is the MSB, followed by the LSB so the value needs
> > to be byte swapped.
> >
> > Also, the ADC actually has a delay of one clock on the SPI bus. Read three
> > bytes to get the last bit.
> >
>
> Can you show example of what is read and what is expected to be a correct value?
> Because it seems I have been reported with similar issue on other TI
> ADC chip [1]. Perhaps we have to fix all of them?
>
> [1]: https://github.com/edison-fw/meta-intel-edison/issues/108

Also, forgot to mention that TI ADC are 16 bit word, so, we need to
read two u16 rather then bytes.

Some configuration won't allow to do byte reads.

> > Fixes: 8dd2d7c0fed7 ("iio: adc: Add driver for the TI ADS8344 A/DC chips")
> > Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Alexandre Belloni April 17, 2020, 11:13 a.m. UTC | #3
On 17/04/2020 13:47:33+0300, Andy Shevchenko wrote:
> On Fri, Apr 17, 2020 at 1:44 PM Andy Shevchenko
> <andy.shevchenko@gmail.com> wrote:
> >
> > On Thu, Apr 16, 2020 at 11:55 PM Alexandre Belloni
> > <alexandre.belloni@bootlin.com> wrote:
> > >
> > > The first received byte is the MSB, followed by the LSB so the value needs
> > > to be byte swapped.
> > >
> > > Also, the ADC actually has a delay of one clock on the SPI bus. Read three
> > > bytes to get the last bit.
> > >
> >
> > Can you show example of what is read and what is expected to be a correct value?
> > Because it seems I have been reported with similar issue on other TI
> > ADC chip [1]. Perhaps we have to fix all of them?
> >
> > [1]: https://github.com/edison-fw/meta-intel-edison/issues/108
> 
> Also, forgot to mention that TI ADC are 16 bit word, so, we need to
> read two u16 rather then bytes.
> 
> Some configuration won't allow to do byte reads.
> 

Both ADC families are not related, I don't think this is your issue. The
ADS8344 was from Burr-Brown.
Andy Shevchenko April 17, 2020, 1:43 p.m. UTC | #4
On Fri, Apr 17, 2020 at 2:13 PM Alexandre Belloni
<alexandre.belloni@bootlin.com> wrote:
> On 17/04/2020 13:47:33+0300, Andy Shevchenko wrote:
> > On Fri, Apr 17, 2020 at 1:44 PM Andy Shevchenko
> > <andy.shevchenko@gmail.com> wrote:
> > > On Thu, Apr 16, 2020 at 11:55 PM Alexandre Belloni
> > > <alexandre.belloni@bootlin.com> wrote:

> Both ADC families are not related, I don't think this is your issue. The
> ADS8344 was from Burr-Brown.

Thanks for clarification.
Andy Shevchenko April 17, 2020, 1:45 p.m. UTC | #5
On Thu, Apr 16, 2020 at 11:55 PM Alexandre Belloni
<alexandre.belloni@bootlin.com> wrote:
>
> The first received byte is the MSB, followed by the LSB so the value needs
> to be byte swapped.
>
> Also, the ADC actually has a delay of one clock on the SPI bus. Read three
> bytes to get the last bit.

> +       return adc->rx_buf[0] << 9 | adc->rx_buf[1] << 1 | adc->rx_buf[2] >> 7;

I just realize, isn't it an open coded variant of ror() / rol()?
Alexandre Belloni April 17, 2020, 2:23 p.m. UTC | #6
On 17/04/2020 16:45:05+0300, Andy Shevchenko wrote:
> On Thu, Apr 16, 2020 at 11:55 PM Alexandre Belloni
> <alexandre.belloni@bootlin.com> wrote:
> >
> > The first received byte is the MSB, followed by the LSB so the value needs
> > to be byte swapped.
> >
> > Also, the ADC actually has a delay of one clock on the SPI bus. Read three
> > bytes to get the last bit.
> 
> > +       return adc->rx_buf[0] << 9 | adc->rx_buf[1] << 1 | adc->rx_buf[2] >> 7;
> 
> I just realize, isn't it an open coded variant of ror() / rol()?
> 

No, this byteswaps and rotates.
Jonathan Cameron April 18, 2020, 3:06 p.m. UTC | #7
On Thu, 16 Apr 2020 22:54:27 +0200
Alexandre Belloni <alexandre.belloni@bootlin.com> wrote:

> The first received byte is the MSB, followed by the LSB so the value needs
> to be byte swapped.
> 
> Also, the ADC actually has a delay of one clock on the SPI bus. Read three
> bytes to get the last bit.
> 
> Fixes: 8dd2d7c0fed7 ("iio: adc: Add driver for the TI ADS8344 A/DC chips")
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

Applied to the fixes-togreg branch of iio.git.  Marked for stable.

Random aside that I'll probably forget to clean up.

Driver includes iio/buffer.h and doesn't use it...

Thanks,

Jonathan


> ---
>  drivers/iio/adc/ti-ads8344.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iio/adc/ti-ads8344.c b/drivers/iio/adc/ti-ads8344.c
> index 9a460807d46d..abe4b56c847c 100644
> --- a/drivers/iio/adc/ti-ads8344.c
> +++ b/drivers/iio/adc/ti-ads8344.c
> @@ -29,7 +29,7 @@ struct ads8344 {
>  	struct mutex lock;
>  
>  	u8 tx_buf ____cacheline_aligned;
> -	u16 rx_buf;
> +	u8 rx_buf[3];
>  };
>  
>  #define ADS8344_VOLTAGE_CHANNEL(chan, si)				\
> @@ -89,11 +89,11 @@ static int ads8344_adc_conversion(struct ads8344 *adc, int channel,
>  
>  	udelay(9);
>  
> -	ret = spi_read(spi, &adc->rx_buf, 2);
> +	ret = spi_read(spi, adc->rx_buf, sizeof(adc->rx_buf));
>  	if (ret)
>  		return ret;
>  
> -	return adc->rx_buf;
> +	return adc->rx_buf[0] << 9 | adc->rx_buf[1] << 1 | adc->rx_buf[2] >> 7;
>  }
>  
>  static int ads8344_read_raw(struct iio_dev *iio,
diff mbox series

Patch

diff --git a/drivers/iio/adc/ti-ads8344.c b/drivers/iio/adc/ti-ads8344.c
index 9a460807d46d..abe4b56c847c 100644
--- a/drivers/iio/adc/ti-ads8344.c
+++ b/drivers/iio/adc/ti-ads8344.c
@@ -29,7 +29,7 @@  struct ads8344 {
 	struct mutex lock;
 
 	u8 tx_buf ____cacheline_aligned;
-	u16 rx_buf;
+	u8 rx_buf[3];
 };
 
 #define ADS8344_VOLTAGE_CHANNEL(chan, si)				\
@@ -89,11 +89,11 @@  static int ads8344_adc_conversion(struct ads8344 *adc, int channel,
 
 	udelay(9);
 
-	ret = spi_read(spi, &adc->rx_buf, 2);
+	ret = spi_read(spi, adc->rx_buf, sizeof(adc->rx_buf));
 	if (ret)
 		return ret;
 
-	return adc->rx_buf;
+	return adc->rx_buf[0] << 9 | adc->rx_buf[1] << 1 | adc->rx_buf[2] >> 7;
 }
 
 static int ads8344_read_raw(struct iio_dev *iio,