On Tue, May 3, 2022 at 10:59 AM Jonathan Cameron <jic23@kernel.org> wrote: > > From: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > ____cacheline_aligned is an insufficient guarantee for non-coherent DMA > on platforms with 128 byte cachelines above L1. Switch to the updated > IIO_ALIGN definition. > > Update the comment to include 'may'. > > Fixes: 131497acd88a ("iio: add ad5761 DAC driver") > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ricardo Ribalda <ribalda@chromium.org> > --- > drivers/iio/dac/ad5761.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/iio/dac/ad5761.c b/drivers/iio/dac/ad5761.c > index 4cb8471db81e..2f493f9ae2d2 100644 > --- a/drivers/iio/dac/ad5761.c > +++ b/drivers/iio/dac/ad5761.c > @@ -70,13 +70,13 @@ struct ad5761_state { > enum ad5761_voltage_range range; > > /* > - * DMA (thus cache coherency maintenance) requires the > + * DMA (thus cache coherency maintenance) may require the > * transfer buffers to live in their own cache lines. > */ > union { > __be32 d32; > u8 d8[4]; > - } data[3] ____cacheline_aligned; > + } data[3] __aligned(IIO_ALIGN); > }; > > static const struct ad5761_range_params ad5761_range_params[] = { > -- > 2.36.0 >
diff --git a/drivers/iio/dac/ad5761.c b/drivers/iio/dac/ad5761.c index 4cb8471db81e..2f493f9ae2d2 100644 --- a/drivers/iio/dac/ad5761.c +++ b/drivers/iio/dac/ad5761.c @@ -70,13 +70,13 @@ struct ad5761_state { enum ad5761_voltage_range range; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[3] ____cacheline_aligned; + } data[3] __aligned(IIO_ALIGN); }; static const struct ad5761_range_params ad5761_range_params[] = {