| Message ID | 20230117135137.1735536-3-haibo.chen@nxp.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | add imx93 adc support | expand |
On Tue, 17 Jan 2023 21:51:36 +0800 haibo.chen@nxp.com wrote: > From: Haibo Chen <haibo.chen@nxp.com> > > The IMX93 SoC has a new ADC IP, so add binding documentation > for NXP IMX93 ADC. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Applied, Thanks, Jonathan > --- > .../bindings/iio/adc/nxp,imx93-adc.yaml | 81 +++++++++++++++++++ > 1 file changed, 81 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml > > diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml > new file mode 100644 > index 000000000000..dacc526dc695 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/adc/nxp,imx93-adc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP iMX93 ADC > + > +maintainers: > + - Haibo Chen <haibo.chen@nxp.com> > + > +description: > + The ADC on iMX93 is a 8-channel 12-bit 1MS/s ADC with 4 channels > + connected to pins. it support normal and inject mode, include > + One-Shot and Scan (continuous) conversions. Programmable DMA > + enables for each channel Also this ADC contain alternate analog > + watchdog thresholds, select threshold through input ports. And > + also has Self-test logic and Software-initiated calibration. > + > +properties: > + compatible: > + const: nxp,imx93-adc > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: WDGnL, watchdog threshold interrupt requests. > + - description: WDGnH, watchdog threshold interrupt requests. > + - description: normal conversion, include EOC (End of Conversion), > + ECH (End of Chain), JEOC (End of Injected Conversion) and > + JECH (End of injected Chain). > + - description: Self-testing Interrupts. > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: ipg > + > + vref-supply: > + description: > + The reference voltage which used to establish channel scaling. > + > + "#io-channel-cells": > + const: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - vref-supply > + - "#io-channel-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/imx93-clock.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + adc@44530000 { > + compatible = "nxp,imx93-adc"; > + reg = <0x44530000 0x10000>; > + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX93_CLK_ADC1_GATE>; > + clock-names = "ipg"; > + vref-supply = <®_vref_1v8>; > + #io-channel-cells = <1>; > + }; > + }; > +...
diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml new file mode 100644 index 000000000000..dacc526dc695 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nxp,imx93-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP iMX93 ADC + +maintainers: + - Haibo Chen <haibo.chen@nxp.com> + +description: + The ADC on iMX93 is a 8-channel 12-bit 1MS/s ADC with 4 channels + connected to pins. it support normal and inject mode, include + One-Shot and Scan (continuous) conversions. Programmable DMA + enables for each channel Also this ADC contain alternate analog + watchdog thresholds, select threshold through input ports. And + also has Self-test logic and Software-initiated calibration. + +properties: + compatible: + const: nxp,imx93-adc + + reg: + maxItems: 1 + + interrupts: + items: + - description: WDGnL, watchdog threshold interrupt requests. + - description: WDGnH, watchdog threshold interrupt requests. + - description: normal conversion, include EOC (End of Conversion), + ECH (End of Chain), JEOC (End of Injected Conversion) and + JECH (End of injected Chain). + - description: Self-testing Interrupts. + + clocks: + maxItems: 1 + + clock-names: + const: ipg + + vref-supply: + description: + The reference voltage which used to establish channel scaling. + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - vref-supply + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx93-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + soc { + #address-cells = <1>; + #size-cells = <1>; + adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + vref-supply = <®_vref_1v8>; + #io-channel-cells = <1>; + }; + }; +...