From patchwork Sun Mar 12 21:23:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 13171872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0479EC74A4B for ; Sun, 12 Mar 2023 21:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231276AbjCLVYC (ORCPT ); Sun, 12 Mar 2023 17:24:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230274AbjCLVYC (ORCPT ); Sun, 12 Mar 2023 17:24:02 -0400 Received: from mail-qt1-x834.google.com (mail-qt1-x834.google.com [IPv6:2607:f8b0:4864:20::834]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9FFE2D165 for ; Sun, 12 Mar 2023 14:23:59 -0700 (PDT) Received: by mail-qt1-x834.google.com with SMTP id w23so11421566qtn.6 for ; Sun, 12 Mar 2023 14:23:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678656239; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=ZVLyQ0XiKSvnucCxXN1dJowGWmlgB/Dt3IZETGB50oM=; b=NZwlJLjToy+H13MwnYz3wpVEi3eqcyI3Ky/Z95chVi1Etbb7yll674a2Y2UmTnpnmX tWd2uorn3U/JuT9zzPi9GmyVOjdMmGBCP0opBRpZGY7fnpIJzGuEX2F/RvENibzPZhix T3xaDhFQxPl2+HZSt7MphB9HbflbScriwBEW+c7fgfgV3KgqCKNlYtb3keBmvPRCRl4n 6xzHBHiHz70dAsqYR307Aee8/G/kQ6m2JPlQ7AQsItuaZabiNL7EONHNOPi/fBmb+Dey EBmu2HenQPEd7+/FcfWmlOR5R9ZKizQ394fe6zjr7yjMx5Tu7Np27KHNlF0T+9XQPBsz 1rMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678656239; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ZVLyQ0XiKSvnucCxXN1dJowGWmlgB/Dt3IZETGB50oM=; b=cjNkUGqjgEiQZcFgGabczPPp/pIq7dWwuLP1+A0JkV+NK2GjE3makNs1Ga/fx0fABc lc4/lWRTPHYfERL2g5jTHaTlKfFQVgGYMhslTYfTQxx7T+pY7X+ZlMmIWxM7fZ2U/LWg bkbhEZK2ur4eNCUa6+XxJuNeFLUDZl6srsyoXmVJZP3WKN1tuQ59BoSUuWwoUcWizEPl AgnIRywoxQoQLDHPKrX5QZX77hvTU8CKWWBqA4AGYxRpMWWwuI0o7i+2KyB7VO4Okx+g LsR+p5BUgGYjGcsIlVnsGYUyN/eLMeOhhVRE7EV08LSEDb0pIa4QErpelt01lJPK6CfR UH9g== X-Gm-Message-State: AO0yUKWVM66ZlRdTENBoEPO8y7eNrERy9cKvRgvEiXUTLP3GdZUrJSzS XTqA94eNBYnvMwVVVKUOQloZXkbuhi9EY3fJ0U0= X-Google-Smtp-Source: AK7set/3JWlfc/2ZRHjNketi/SeZBKZTydDQmqOhfdBs0PJV6yIC3rVOfTjHRFuIIEip70Ig9+V9vg== X-Received: by 2002:a05:622a:178b:b0:3bf:daae:7f34 with SMTP id s11-20020a05622a178b00b003bfdaae7f34mr26411301qtk.41.1678656238686; Sun, 12 Mar 2023 14:23:58 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id j23-20020ac85517000000b0039cc0fbdb61sm4285274qtq.53.2023.03.12.14.23.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 14:23:58 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: jic23@kernel.org, linux-kernel@vger.kernel.org, William Breathitt Gray , stable@vger.kernel.org Subject: [PATCH v2] counter: 104-quad-8: Fix race condition between FLAG and CNTR reads Date: Sun, 12 Mar 2023 17:23:47 -0400 Message-Id: <20230312212347.129756-1-william.gray@linaro.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org The Counter (CNTR) register is 24 bits wide, but we can have an effective 25-bit count value by setting bit 24 to the XOR of the Borrow flag and Carry flag. The flags can be read from the FLAG register, but a race condition exists: the Borrow flag and Carry flag are instantaneous and could change by the time the count value is read from the CNTR register. Since the race condition could result in an incorrect 25-bit count value, remove support for 25-bit count values from this driver; hard-coded maximum count values are replaced by a LS7267_CNTR_MAX define for consistency and clarity. Fixes: 28e5d3bb0325 ("iio: 104-quad-8: Add IIO support for the ACCES 104-QUAD-8") Cc: stable@vger.kernel.org Signed-off-by: William Breathitt Gray --- Changes in v2: - Correct Fixes tag line in commit description - Add Cc tag line for stable@vger.kernel.org drivers/counter/104-quad-8.c | 29 +++++++---------------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index deed4afadb29..dba04b5e80b7 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -97,10 +97,6 @@ struct quad8 { struct quad8_reg __iomem *reg; }; -/* Borrow Toggle flip-flop */ -#define QUAD8_FLAG_BT BIT(0) -/* Carry Toggle flip-flop */ -#define QUAD8_FLAG_CT BIT(1) /* Error flag */ #define QUAD8_FLAG_E BIT(4) /* Up/Down flag */ @@ -133,6 +129,9 @@ struct quad8 { #define QUAD8_CMR_QUADRATURE_X2 0x10 #define QUAD8_CMR_QUADRATURE_X4 0x18 +/* Each Counter is 24 bits wide */ +#define LS7267_CNTR_MAX GENMASK(23, 0) + static int quad8_signal_read(struct counter_device *counter, struct counter_signal *signal, enum counter_signal_level *level) @@ -156,19 +155,9 @@ static int quad8_count_read(struct counter_device *counter, { struct quad8 *const priv = counter_priv(counter); struct channel_reg __iomem *const chan = priv->reg->channel + count->id; - unsigned int flags; - unsigned int borrow; - unsigned int carry; unsigned long irqflags; int i; - flags = ioread8(&chan->control); - borrow = flags & QUAD8_FLAG_BT; - carry = !!(flags & QUAD8_FLAG_CT); - - /* Borrow XOR Carry effectively doubles count range */ - *val = (unsigned long)(borrow ^ carry) << 24; - spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer; transfer Counter to Output Latch */ @@ -191,8 +180,7 @@ static int quad8_count_write(struct counter_device *counter, unsigned long irqflags; int i; - /* Only 24-bit values are supported */ - if (val > 0xFFFFFF) + if (val > LS7267_CNTR_MAX) return -ERANGE; spin_lock_irqsave(&priv->lock, irqflags); @@ -806,8 +794,7 @@ static int quad8_count_preset_write(struct counter_device *counter, struct quad8 *const priv = counter_priv(counter); unsigned long irqflags; - /* Only 24-bit values are supported */ - if (preset > 0xFFFFFF) + if (preset > LS7267_CNTR_MAX) return -ERANGE; spin_lock_irqsave(&priv->lock, irqflags); @@ -834,8 +821,7 @@ static int quad8_count_ceiling_read(struct counter_device *counter, *ceiling = priv->preset[count->id]; break; default: - /* By default 0x1FFFFFF (25 bits unsigned) is maximum count */ - *ceiling = 0x1FFFFFF; + *ceiling = LS7267_CNTR_MAX; break; } @@ -850,8 +836,7 @@ static int quad8_count_ceiling_write(struct counter_device *counter, struct quad8 *const priv = counter_priv(counter); unsigned long irqflags; - /* Only 24-bit values are supported */ - if (ceiling > 0xFFFFFF) + if (ceiling > LS7267_CNTR_MAX) return -ERANGE; spin_lock_irqsave(&priv->lock, irqflags);