| Message ID | 20230530075311.400686-6-fl.scratchpad@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Fix ad7192 driver issues | expand |
On Tue, May 30, 2023 at 09:53:11AM +0200, fl.scratchpad@gmail.com wrote: > From: Fabrizio Lamarque <fl.scratchpad@gmail.com> > > AD7192 supports external clock sources, generated by a digital clock > source or a crystal oscillator, or internally generated clock option > without external components. > > Describe choice between internal and external clock, crystal or external > oscillator, and internal clock output enable. > > Signed-off-by: Fabrizio Lamarque <fl.scratchpad@gmail.com> > --- > .../bindings/iio/adc/adi,ad7192.yaml | 27 ++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > index 16def2985ab4..f7ecfd65ad80 100644 > --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > @@ -32,7 +32,8 @@ properties: > > clocks: > maxItems: 1 > - description: phandle to the master clock (mclk) > + description: | > + Master clock (mclk). If not set, internal clock is used. > > clock-names: > items: > @@ -50,6 +51,17 @@ properties: > vref-supply: > description: VRef voltage supply > > + adi,clock-xtal: > + description: | > + Select whether an external crystal oscillator or an external > + clock is applied as master (mclk) clock. > + type: boolean Am I being daft, or are these the same thing? If they are not, and use different input pins, I think it should be explained as it not clear. Could you explain why we actually care that the source is a xtal versus it being mclk, and why just having master clock is not sufficient? > + adi,int-clock-output-enable: > + description: | > + When internal clock is selected, this bit enables clock out pin. > + type: boolean And this one makes you a clock provider, so the devices advocate position would be that you know that this bit should be set if "clocks" is not present and a consumer requests a clock. I don't seem to have got the driver patches (at least not in this mailbox), so I have got no information on how you've actually implemented this. Cheers, Conor. > + > adi,rejection-60-Hz-enable: > description: | > This bit enables a notch at 60 Hz when the first notch of the sinc > @@ -84,11 +96,12 @@ properties: > description: see Documentation/devicetree/bindings/iio/adc/adc.yaml > type: boolean > > +dependencies: > + adi,clock-xtal: ['clocks', 'clock-names'] > + > required: > - compatible > - reg > - - clocks > - - clock-names > - interrupts > - dvdd-supply > - avdd-supply > @@ -98,6 +111,13 @@ required: > > allOf: > - $ref: /schemas/spi/spi-peripheral-props.yaml# > + - if: > + required: > + - clocks > + - clock-names > + then: > + properties: > + adi,int-clock-output-enable: false > > unevaluatedProperties: false > > @@ -115,6 +135,7 @@ examples: > spi-cpha; > clocks = <&ad7192_mclk>; > clock-names = "mclk"; > + adi,clock-xtal; > interrupts = <25 0x2>; > interrupt-parent = <&gpio>; > dvdd-supply = <&dvdd>; > -- > 2.34.1 >
On Tue, May 30, 2023 at 7:22 PM Conor Dooley <conor@kernel.org> wrote: > > On Tue, May 30, 2023 at 09:53:11AM +0200, fl.scratchpad@gmail.com wrote: > > From: Fabrizio Lamarque <fl.scratchpad@gmail.com> > > > > AD7192 supports external clock sources, generated by a digital clock > > source or a crystal oscillator, or internally generated clock option > > without external components. > > > > Describe choice between internal and external clock, crystal or external > > oscillator, and internal clock output enable. > > > > Signed-off-by: Fabrizio Lamarque <fl.scratchpad@gmail.com> > > --- > > .../bindings/iio/adc/adi,ad7192.yaml | 27 ++++++++++++++++--- > > 1 file changed, 24 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > > index 16def2985ab4..f7ecfd65ad80 100644 > > --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > > @@ -32,7 +32,8 @@ properties: > > > > clocks: > > maxItems: 1 > > - description: phandle to the master clock (mclk) > > + description: | > > + Master clock (mclk). If not set, internal clock is used. > > > > clock-names: > > items: > > @@ -50,6 +51,17 @@ properties: > > vref-supply: > > description: VRef voltage supply > > > > + adi,clock-xtal: > > + description: | > > + Select whether an external crystal oscillator or an external > > + clock is applied as master (mclk) clock. > > + type: boolean > > Am I being daft, or are these the same thing? If they are not, and use > different input pins, I think it should be explained as it not clear. > Could you explain why we actually care that the source is a xtal versus > it being mclk, and why just having master clock is not sufficient? I may revise the description as follows. Feel free to add your suggestions in case it is still not clear enough. "Select whether an external crystal oscillator between MCLK1 and MCLK2 or an external CMOS-compatible clock on MCLK2 is used as master clock". This is used to properly set CLK0 and CLK1 bits in the MODE register. I guess most applications would use an external crystal or internal clock. The external digital clock would allow synchronization of multiple ADCs, > > > + adi,int-clock-output-enable: > > + description: | > > + When internal clock is selected, this bit enables clock out pin. > > + type: boolean > > And this one makes you a clock provider, so the devices advocate > position would be that you know that this bit should be set if > "clocks" is not present and a consumer requests a clock. > I don't seem to have got the driver patches (at least not in this > mailbox), so I have got no information on how you've actually implemented > this. I see... When this bit is set, the AD7192 node should also be a clock provider. The clock is output on MCLK2 pin, hence it can be used with internally generated clock only. I tend to dislike the idea of a "conditional clock provider". Also, I'd guess there is a very limited usage of a low precision clock output for synchronization purposes between multiple ADCs. In the remote case, I would rather use a precise, dedicated external digital clock. Would you agree if I remove the related lines from the change set? If not, I kindly ask for your suggestions. The existing implementation from AD already includes all these configurations (there are no driver patches, the proposed changes are just related to documentation). Thank you! Fabrizio > > Cheers, > Conor. > > > + > > adi,rejection-60-Hz-enable: > > description: | > > This bit enables a notch at 60 Hz when the first notch of the sinc > > @@ -84,11 +96,12 @@ properties: > > description: see Documentation/devicetree/bindings/iio/adc/adc.yaml > > type: boolean > > > > +dependencies: > > + adi,clock-xtal: ['clocks', 'clock-names'] > > + > > required: > > - compatible > > - reg > > - - clocks > > - - clock-names > > - interrupts > > - dvdd-supply > > - avdd-supply > > @@ -98,6 +111,13 @@ required: > > > > allOf: > > - $ref: /schemas/spi/spi-peripheral-props.yaml# > > + - if: > > + required: > > + - clocks > > + - clock-names > > + then: > > + properties: > > + adi,int-clock-output-enable: false > > > > unevaluatedProperties: false > > > > @@ -115,6 +135,7 @@ examples: > > spi-cpha; > > clocks = <&ad7192_mclk>; > > clock-names = "mclk"; > > + adi,clock-xtal; > > interrupts = <25 0x2>; > > interrupt-parent = <&gpio>; > > dvdd-supply = <&dvdd>; > > -- > > 2.34.1 > >
On 31/05/2023 08:59, Fabrizio Lamarque wrote: > On Tue, May 30, 2023 at 7:22 PM Conor Dooley <conor@kernel.org> wrote: >> >> On Tue, May 30, 2023 at 09:53:11AM +0200, fl.scratchpad@gmail.com wrote: >>> From: Fabrizio Lamarque <fl.scratchpad@gmail.com> >>> >>> AD7192 supports external clock sources, generated by a digital clock >>> source or a crystal oscillator, or internally generated clock option >>> without external components. >>> >>> Describe choice between internal and external clock, crystal or external >>> oscillator, and internal clock output enable. >>> >>> Signed-off-by: Fabrizio Lamarque <fl.scratchpad@gmail.com> >>> --- >>> .../bindings/iio/adc/adi,ad7192.yaml | 27 ++++++++++++++++--- >>> 1 file changed, 24 insertions(+), 3 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml >>> index 16def2985ab4..f7ecfd65ad80 100644 >>> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml >>> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml >>> @@ -32,7 +32,8 @@ properties: >>> >>> clocks: >>> maxItems: 1 >>> - description: phandle to the master clock (mclk) >>> + description: | >>> + Master clock (mclk). If not set, internal clock is used. >>> >>> clock-names: >>> items: >>> @@ -50,6 +51,17 @@ properties: >>> vref-supply: >>> description: VRef voltage supply >>> >>> + adi,clock-xtal: >>> + description: | >>> + Select whether an external crystal oscillator or an external >>> + clock is applied as master (mclk) clock. >>> + type: boolean >> >> Am I being daft, or are these the same thing? If they are not, and use >> different input pins, I think it should be explained as it not clear. >> Could you explain why we actually care that the source is a xtal versus >> it being mclk, and why just having master clock is not sufficient? > > I may revise the description as follows. Feel free to add your suggestions > in case it is still not clear enough. > > "Select whether an external crystal oscillator between MCLK1 and MCLK2 or > an external CMOS-compatible clock on MCLK2 is used as master clock". > > This is used to properly set CLK0 and CLK1 bits in the MODE register. > I guess most applications would use an external crystal or internal clock. > The external digital clock would allow synchronization of multiple ADCs, Description confuses me. Why would it matter what type of clock you have as input - external crystal oscillator or external CMOS-compatible clock? Later you refer to "internal", so maybe you meant here also internal for one of the options? > >> >>> + adi,int-clock-output-enable: >>> + description: | >>> + When internal clock is selected, this bit enables clock out pin. >>> + type: boolean >> >> And this one makes you a clock provider, so the devices advocate >> position would be that you know that this bit should be set if >> "clocks" is not present and a consumer requests a clock. >> I don't seem to have got the driver patches (at least not in this >> mailbox), so I have got no information on how you've actually implemented >> this. > > I see... When this bit is set, the AD7192 node should also be a clock provider. > The clock is output on MCLK2 pin, hence it can be used with internally > generated clock only. > I tend to dislike the idea of a "conditional clock provider". Also, I'd guess Either this is a clock provider via common clock framework or is not. Don't re-implement clock provider via other properties but just skip such feature. Best regards, Krzysztof
On Wed, May 31, 2023 at 9:14 AM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 31/05/2023 08:59, Fabrizio Lamarque wrote: > > On Tue, May 30, 2023 at 7:22 PM Conor Dooley <conor@kernel.org> wrote: > >> > >> On Tue, May 30, 2023 at 09:53:11AM +0200, fl.scratchpad@gmail.com wrote: > >>> From: Fabrizio Lamarque <fl.scratchpad@gmail.com> > >>> > >>> AD7192 supports external clock sources, generated by a digital clock > >>> source or a crystal oscillator, or internally generated clock option > >>> without external components. > >>> > >>> Describe choice between internal and external clock, crystal or external > >>> oscillator, and internal clock output enable. > >>> > >>> Signed-off-by: Fabrizio Lamarque <fl.scratchpad@gmail.com> > >>> --- > >>> .../bindings/iio/adc/adi,ad7192.yaml | 27 ++++++++++++++++--- > >>> 1 file changed, 24 insertions(+), 3 deletions(-) > >>> > >>> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > >>> index 16def2985ab4..f7ecfd65ad80 100644 > >>> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > >>> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > >>> @@ -32,7 +32,8 @@ properties: > >>> > >>> clocks: > >>> maxItems: 1 > >>> - description: phandle to the master clock (mclk) > >>> + description: | > >>> + Master clock (mclk). If not set, internal clock is used. > >>> > >>> clock-names: > >>> items: > >>> @@ -50,6 +51,17 @@ properties: > >>> vref-supply: > >>> description: VRef voltage supply > >>> > >>> + adi,clock-xtal: > >>> + description: | > >>> + Select whether an external crystal oscillator or an external > >>> + clock is applied as master (mclk) clock. > >>> + type: boolean > >> > >> Am I being daft, or are these the same thing? If they are not, and use > >> different input pins, I think it should be explained as it not clear. > >> Could you explain why we actually care that the source is a xtal versus > >> it being mclk, and why just having master clock is not sufficient? > > > > I may revise the description as follows. Feel free to add your suggestions > > in case it is still not clear enough. > > > > "Select whether an external crystal oscillator between MCLK1 and MCLK2 or > > an external CMOS-compatible clock on MCLK2 is used as master clock". > > > > This is used to properly set CLK0 and CLK1 bits in the MODE register. > > I guess most applications would use an external crystal or internal clock. > > The external digital clock would allow synchronization of multiple ADCs, > > Description confuses me. Why would it matter what type of clock you have > as input - external crystal oscillator or external CMOS-compatible > clock? Later you refer to "internal", so maybe you meant here also > internal for one of the options? The AD7192 needs to be configured according to the type of external clock that is applied on MCLK1/MCLK2 pins in order to activate the correct circuitry. Here are some citations from the datasheet: MCLK2 pin description: "The AD7192 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7192 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected." Each of these clock modes have to be configured via AD7192 mode register. (Clock source configuration bits, mode register, CLK0 and CLK1). Here is their description from datasheet: "Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7192 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7192." The choice between internal clock, external crystal oscillator or external CMOS digital clock is a decision of the HW designer driven by noise rejection, synchronization, and cost requirements. If possible, I kindly ask you suggestions on how to adjust the description so that it would be cleaner. > > > > >> > >>> + adi,int-clock-output-enable: > >>> + description: | > >>> + When internal clock is selected, this bit enables clock out pin. > >>> + type: boolean > >> > >> And this one makes you a clock provider, so the devices advocate > >> position would be that you know that this bit should be set if > >> "clocks" is not present and a consumer requests a clock. > >> I don't seem to have got the driver patches (at least not in this > >> mailbox), so I have got no information on how you've actually implemented > >> this. > > > > I see... When this bit is set, the AD7192 node should also be a clock provider. > > The clock is output on MCLK2 pin, hence it can be used with internally > > generated clock only. > > I tend to dislike the idea of a "conditional clock provider". Also, I'd guess > > Either this is a clock provider via common clock framework or is not. > Don't re-implement clock provider via other properties but just skip > such feature. Ok, I understand. I will remove the bit from the patch in V4. Thank you. The bit was already existing upstream in the driver, but I would just drop the change in documentation without any additional patch that removes it from the driver. Best regards, Fabrizio Lamarque
On Wed, May 31, 2023 at 11:40:08AM +0200, Fabrizio Lamarque wrote: > On Wed, May 31, 2023 at 9:14 AM Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: > > > > On 31/05/2023 08:59, Fabrizio Lamarque wrote: > > > On Tue, May 30, 2023 at 7:22 PM Conor Dooley <conor@kernel.org> wrote: > > >> > > >> On Tue, May 30, 2023 at 09:53:11AM +0200, fl.scratchpad@gmail.com wrote: > > >>> From: Fabrizio Lamarque <fl.scratchpad@gmail.com> > > >>> > > >>> AD7192 supports external clock sources, generated by a digital clock > > >>> source or a crystal oscillator, or internally generated clock option > > >>> without external components. > > >>> > > >>> Describe choice between internal and external clock, crystal or external > > >>> oscillator, and internal clock output enable. > > >>> > > >>> Signed-off-by: Fabrizio Lamarque <fl.scratchpad@gmail.com> > > >>> --- > > >>> .../bindings/iio/adc/adi,ad7192.yaml | 27 ++++++++++++++++--- > > >>> 1 file changed, 24 insertions(+), 3 deletions(-) > > >>> > > >>> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > > >>> index 16def2985ab4..f7ecfd65ad80 100644 > > >>> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > > >>> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > > >>> @@ -32,7 +32,8 @@ properties: > > >>> > > >>> clocks: > > >>> maxItems: 1 > > >>> - description: phandle to the master clock (mclk) > > >>> + description: | > > >>> + Master clock (mclk). If not set, internal clock is used. > > >>> > > >>> clock-names: > > >>> items: > > >>> @@ -50,6 +51,17 @@ properties: > > >>> vref-supply: > > >>> description: VRef voltage supply > > >>> > > >>> + adi,clock-xtal: > > >>> + description: | > > >>> + Select whether an external crystal oscillator or an external > > >>> + clock is applied as master (mclk) clock. > > >>> + type: boolean > > >> > > >> Am I being daft, or are these the same thing? If they are not, and use > > >> different input pins, I think it should be explained as it not clear. > > >> Could you explain why we actually care that the source is a xtal versus > > >> it being mclk, and why just having master clock is not sufficient? > > > > > > I may revise the description as follows. Feel free to add your suggestions > > > in case it is still not clear enough. > > > > > > "Select whether an external crystal oscillator between MCLK1 and MCLK2 or > > > an external CMOS-compatible clock on MCLK2 is used as master clock". > > > > > > This is used to properly set CLK0 and CLK1 bits in the MODE register. > > > I guess most applications would use an external crystal or internal clock. > > > The external digital clock would allow synchronization of multiple ADCs, > > > > Description confuses me. Why would it matter what type of clock you have > > as input - external crystal oscillator or external CMOS-compatible > > clock? Later you refer to "internal", so maybe you meant here also > > internal for one of the options? > > The AD7192 needs to be configured according to the type of external > clock that is > applied on MCLK1/MCLK2 pins in order to activate the correct circuitry. > > Here are some citations from the datasheet: > > MCLK2 pin description: > "The AD7192 has an internal 4.92 MHz clock. This internal clock can be > made available > on the MCLK2 pin. The clock for the AD7192 can be provided externally > also in the form > of a crystal or external clock. A crystal can be tied across the MCLK1 > and MCLK2 pins. > Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the > MCLK1 pin left unconnected." > > Each of these clock modes have to be configured via AD7192 mode register. > (Clock source configuration bits, mode register, CLK0 and CLK1). > Here is their description from datasheet: > > "Either the on-chip 4.92 MHz clock or an external clock can be used. > The ability to > use an external clock allows several AD7192 devices to be synchronized. Also, > 50 Hz/60 Hz rejection is improved when an accurate external clock > drives the AD7192." > > The choice between internal clock, external crystal oscillator or > external CMOS digital > clock is a decision of the HW designer driven by noise rejection, > synchronization, and > cost requirements. > > If possible, I kindly ask you suggestions on how to adjust the description > so that it would be cleaner. For me at least, I partially wanted it explained so that intimate knowledge of the part was not required to review the binding! To me, the original description is perfectly clear about how the hardware is configured, but nothing says why software needs to actually know about it. I'd be happy if you worked > Each of these clock modes have to be configured via AD7192 mode register. into the description, but perhaps Krzysztof disagrees. Cheers, Conor. > > >>> + adi,int-clock-output-enable: > > >>> + description: | > > >>> + When internal clock is selected, this bit enables clock out pin. > > >>> + type: boolean > > >> > > >> And this one makes you a clock provider, so the devices advocate > > >> position would be that you know that this bit should be set if > > >> "clocks" is not present and a consumer requests a clock. > > >> I don't seem to have got the driver patches (at least not in this > > >> mailbox), so I have got no information on how you've actually implemented > > >> this. > > > > > > I see... When this bit is set, the AD7192 node should also be a clock provider. > > > The clock is output on MCLK2 pin, hence it can be used with internally > > > generated clock only. > > > I tend to dislike the idea of a "conditional clock provider". Also, I'd guess > > > > Either this is a clock provider via common clock framework or is not. > > Don't re-implement clock provider via other properties but just skip > > such feature. > > Ok, I understand. I will remove the bit from the patch in V4. Thank you. > > The bit was already existing upstream in the driver, but I would just drop > the change in documentation without any additional patch that removes it > from the driver. > > Best regards, > Fabrizio Lamarque
On Wed, May 31, 2023 at 9:24 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 31/05/2023 11:40, Fabrizio Lamarque wrote: > > On Wed, May 31, 2023 at 9:14 AM Krzysztof Kozlowski > > <krzysztof.kozlowski@linaro.org> wrote: > >> > >> On 31/05/2023 08:59, Fabrizio Lamarque wrote: > >>> On Tue, May 30, 2023 at 7:22 PM Conor Dooley <conor@kernel.org> wrote: > >>>> > >>>> On Tue, May 30, 2023 at 09:53:11AM +0200, fl.scratchpad@gmail.com wrote: > >>>>> From: Fabrizio Lamarque <fl.scratchpad@gmail.com> > >>>>> > >>>>> AD7192 supports external clock sources, generated by a digital clock > >>>>> source or a crystal oscillator, or internally generated clock option > >>>>> without external components. > >>>>> > >>>>> Describe choice between internal and external clock, crystal or external > >>>>> oscillator, and internal clock output enable. > >>>>> > >>>>> Signed-off-by: Fabrizio Lamarque <fl.scratchpad@gmail.com> > >>>>> --- > >>>>> .../bindings/iio/adc/adi,ad7192.yaml | 27 ++++++++++++++++--- > >>>>> 1 file changed, 24 insertions(+), 3 deletions(-) > >>>>> > >>>>> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > >>>>> index 16def2985ab4..f7ecfd65ad80 100644 > >>>>> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > >>>>> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > >>>>> @@ -32,7 +32,8 @@ properties: > >>>>> > >>>>> clocks: > >>>>> maxItems: 1 > >>>>> - description: phandle to the master clock (mclk) > >>>>> + description: | > >>>>> + Master clock (mclk). If not set, internal clock is used. > >>>>> > >>>>> clock-names: > >>>>> items: > >>>>> @@ -50,6 +51,17 @@ properties: > >>>>> vref-supply: > >>>>> description: VRef voltage supply > >>>>> > >>>>> + adi,clock-xtal: > >>>>> + description: | > >>>>> + Select whether an external crystal oscillator or an external > >>>>> + clock is applied as master (mclk) clock. > >>>>> + type: boolean > >>>> > >>>> Am I being daft, or are these the same thing? If they are not, and use > >>>> different input pins, I think it should be explained as it not clear. > >>>> Could you explain why we actually care that the source is a xtal versus > >>>> it being mclk, and why just having master clock is not sufficient? > >>> > >>> I may revise the description as follows. Feel free to add your suggestions > >>> in case it is still not clear enough. > >>> > >>> "Select whether an external crystal oscillator between MCLK1 and MCLK2 or > >>> an external CMOS-compatible clock on MCLK2 is used as master clock". > >>> > >>> This is used to properly set CLK0 and CLK1 bits in the MODE register. > >>> I guess most applications would use an external crystal or internal clock. > >>> The external digital clock would allow synchronization of multiple ADCs, > >> > >> Description confuses me. Why would it matter what type of clock you have > >> as input - external crystal oscillator or external CMOS-compatible > >> clock? Later you refer to "internal", so maybe you meant here also > >> internal for one of the options? > > > > The AD7192 needs to be configured according to the type of external > > clock that is > > applied on MCLK1/MCLK2 pins in order to activate the correct circuitry. > > > > Here are some citations from the datasheet: > > > > MCLK2 pin description: > > "The AD7192 has an internal 4.92 MHz clock. This internal clock can be > > made available > > on the MCLK2 pin. The clock for the AD7192 can be provided externally > > also in the form > > of a crystal or external clock. A crystal can be tied across the MCLK1 > > and MCLK2 pins. > > Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the > > MCLK1 pin left unconnected." > > > > Each of these clock modes have to be configured via AD7192 mode register. > > (Clock source configuration bits, mode register, CLK0 and CLK1). > > Here is their description from datasheet: > > > > "Either the on-chip 4.92 MHz clock or an external clock can be used. > > The ability to > > use an external clock allows several AD7192 devices to be synchronized. Also, > > 50 Hz/60 Hz rejection is improved when an accurate external clock > > drives the AD7192." > > > > The choice between internal clock, external crystal oscillator or > > external CMOS digital > > clock is a decision of the HW designer driven by noise rejection, > > synchronization, and > > cost requirements. > > > > If possible, I kindly ask you suggestions on how to adjust the description > > so that it would be cleaner. > > It's fine. I missed that part that first option requires feeding the > clock through two pins ("and"). Thank you once again. I've reworded the commit message, removed the adi,int-clock-output-enable option and clarified the adi,clock-xtal entry. This would be the new commit message: AD7192 can be clocked from either: - Internal clock - CMOS-compatible clock on MCLK2 - Crystal oscillator on MCLK1 and MCLK2 Each of these modes have to be configured via AD7192 mode register. Describe choice between these clock modes. And this is the new description for adi,clock-xtal: This bit sets external clock mode. When set, master clock is sourced from a crystal connected from MCLK1 to MCLK2. When cleared, a CMOS-compatible clock source is expected on MCLK2. Is this description cleaner? If possible, I kindly ask you for feedback before posting a v4 (with only patch 3/5 and 5/5 since the others have already been applied). Best regards, Fabrizio Lamarque
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index 16def2985ab4..f7ecfd65ad80 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -32,7 +32,8 @@ properties: clocks: maxItems: 1 - description: phandle to the master clock (mclk) + description: | + Master clock (mclk). If not set, internal clock is used. clock-names: items: @@ -50,6 +51,17 @@ properties: vref-supply: description: VRef voltage supply + adi,clock-xtal: + description: | + Select whether an external crystal oscillator or an external + clock is applied as master (mclk) clock. + type: boolean + + adi,int-clock-output-enable: + description: | + When internal clock is selected, this bit enables clock out pin. + type: boolean + adi,rejection-60-Hz-enable: description: | This bit enables a notch at 60 Hz when the first notch of the sinc @@ -84,11 +96,12 @@ properties: description: see Documentation/devicetree/bindings/iio/adc/adc.yaml type: boolean +dependencies: + adi,clock-xtal: ['clocks', 'clock-names'] + required: - compatible - reg - - clocks - - clock-names - interrupts - dvdd-supply - avdd-supply @@ -98,6 +111,13 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + required: + - clocks + - clock-names + then: + properties: + adi,int-clock-output-enable: false unevaluatedProperties: false @@ -115,6 +135,7 @@ examples: spi-cpha; clocks = <&ad7192_mclk>; clock-names = "mclk"; + adi,clock-xtal; interrupts = <25 0x2>; interrupt-parent = <&gpio>; dvdd-supply = <&dvdd>;