[v2,3/3] riscv: dts: sophgo: Add SARADC configuration

Commit Message

Thomas Bonnefille July 5, 2024, 1:42 p.m. UTC

Adds SARADC nodes for the common Successive Approximation Analog to
Digital Converter used in Sophgo CV18xx series SoC.
This patch adds two nodes for the two controllers the board, one in
the Active domain and the other in the No-Die domain.

Signed-off-by: Thomas Bonnefille <[e-mail]>
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi |  8 ++++++++
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi  | 14 ++++++++++++++
 2 files changed, 22 insertions(+)

Patch

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index ec9530972ae2..73abbb6e5363 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -25,3 +25,11 @@  &clint {
 &clk {
 	compatible = "sophgo,cv1800-clk";
 };
+
+&saradc_active {
+	compatible = "sophgo,cv1800b-saradc", "sophgo,cv18xx-saradc";
+};
+
+&saradc_nodie {
+	compatible = "sophgo,cv1800b-saradc", "sophgo,cv18xx-saradc";
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f..752e14fa3d0c 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -133,6 +133,14 @@  portd: gpio-controller@0 {
 			};
 		};
 
+		saradc_active: adc@30f0000 {
+			compatible = "sophgo,cv18xx-saradc";
+			clocks = <&clk CLK_SARADC>;
+			interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x030F0000 0x1000>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@4000000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x04000000 0x10000>;
@@ -297,6 +305,12 @@  sdhci0: mmc@4310000 {
 			status = "disabled";
 		};
 
+		saradc_nodie: adc@502c000 {
+			compatible = "sophgo,cv18xx-saradc";
+			reg = <0x0502C000 0x1000>;
+			status = "disabled";
+		};
+
 		plic: interrupt-controller@70000000 {
 			reg = <0x70000000 0x4000000>;
 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;