| Message ID | 20240819064721.91494-8-aardelean@baylibre.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | iio: adc: ad7606: add support for AD7606C-{16,18} parts | expand |
Hi Alexandru,
kernel test robot noticed the following build warnings:
[auto build test WARNING on jic23-iio/togreg]
[cannot apply to linus/master v6.11-rc4 next-20240819]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Alexandru-Ardelean/iio-adc-ad7606-add-bits-parameter-to-channels-macros/20240819-145028
base: https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
patch link: https://lore.kernel.org/r/20240819064721.91494-8-aardelean%40baylibre.com
patch subject: [PATCH 7/7] iio: adc: ad7606: add support for AD7606C-{16,18} parts
config: i386-buildonly-randconfig-001-20240819 (https://download.01.org/0day-ci/archive/20240819/202408192209.IrTzVL49-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240819/202408192209.IrTzVL49-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408192209.IrTzVL49-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/iio/adc/ad7606.c:796:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
796 | int ret, ch;
| ^
1 warning generated.
vim +/ret +796 drivers/iio/adc/ad7606.c
94168a5789874a Alexandru Ardelean 2024-08-19 790
94168a5789874a Alexandru Ardelean 2024-08-19 791 static int ad7606_sw_mode_setup(struct iio_dev *indio_dev, unsigned int id)
b5d2c422286d62 Alexandru Ardelean 2024-08-19 792 {
36b63bb57295f7 Alexandru Ardelean 2024-08-19 793 unsigned int num_channels = indio_dev->num_channels - 1;
b5d2c422286d62 Alexandru Ardelean 2024-08-19 794 struct ad7606_state *st = iio_priv(indio_dev);
09d11fa081ef17 Alexandru Ardelean 2024-08-19 795 unsigned int *scale_avail_show, num_scales_avail_show;
09d11fa081ef17 Alexandru Ardelean 2024-08-19 @796 int ret, ch;
b5d2c422286d62 Alexandru Ardelean 2024-08-19 797
b5d2c422286d62 Alexandru Ardelean 2024-08-19 798 if (!st->bops->sw_mode_config)
b5d2c422286d62 Alexandru Ardelean 2024-08-19 799 return 0;
b5d2c422286d62 Alexandru Ardelean 2024-08-19 800
b5d2c422286d62 Alexandru Ardelean 2024-08-19 801 st->sw_mode_en = device_property_present(st->dev, "adi,sw-mode");
b5d2c422286d62 Alexandru Ardelean 2024-08-19 802 if (!st->sw_mode_en)
b5d2c422286d62 Alexandru Ardelean 2024-08-19 803 return 0;
b5d2c422286d62 Alexandru Ardelean 2024-08-19 804
09d11fa081ef17 Alexandru Ardelean 2024-08-19 805 indio_dev->info = &ad7606_info_sw_mode;
b5d2c422286d62 Alexandru Ardelean 2024-08-19 806
94168a5789874a Alexandru Ardelean 2024-08-19 807 switch (id) {
94168a5789874a Alexandru Ardelean 2024-08-19 808 case ID_AD7606C_18:
94168a5789874a Alexandru Ardelean 2024-08-19 809 num_scales_avail_show = num_channels;
94168a5789874a Alexandru Ardelean 2024-08-19 810 ret = ad7606c_sw_mode_setup_channels(indio_dev,
94168a5789874a Alexandru Ardelean 2024-08-19 811 ad7606c_18_chan_setup);
94168a5789874a Alexandru Ardelean 2024-08-19 812 break;
94168a5789874a Alexandru Ardelean 2024-08-19 813 case ID_AD7606C_16:
94168a5789874a Alexandru Ardelean 2024-08-19 814 num_scales_avail_show = num_channels;
94168a5789874a Alexandru Ardelean 2024-08-19 815 ret = ad7606c_sw_mode_setup_channels(indio_dev,
94168a5789874a Alexandru Ardelean 2024-08-19 816 ad7606c_16_chan_setup);
94168a5789874a Alexandru Ardelean 2024-08-19 817 break;
94168a5789874a Alexandru Ardelean 2024-08-19 818 default:
94168a5789874a Alexandru Ardelean 2024-08-19 819 num_scales_avail_show = 1;
94168a5789874a Alexandru Ardelean 2024-08-19 820
b5d2c422286d62 Alexandru Ardelean 2024-08-19 821 /* Scale of 0.076293 is only available in sw mode */
b5d2c422286d62 Alexandru Ardelean 2024-08-19 822 /* After reset, in software mode, ±10 V is set by default */
36b63bb57295f7 Alexandru Ardelean 2024-08-19 823 for (ch = 0; ch < num_channels; ch++) {
36b63bb57295f7 Alexandru Ardelean 2024-08-19 824 struct ad7606_chan_scale *cs = &st->chan_scales[ch];
36b63bb57295f7 Alexandru Ardelean 2024-08-19 825
36b63bb57295f7 Alexandru Ardelean 2024-08-19 826 cs->scale_avail = ad7616_sw_scale_avail;
36b63bb57295f7 Alexandru Ardelean 2024-08-19 827 cs->num_scales = ARRAY_SIZE(ad7616_sw_scale_avail);
36b63bb57295f7 Alexandru Ardelean 2024-08-19 828 cs->range = 2;
36b63bb57295f7 Alexandru Ardelean 2024-08-19 829 }
b5d2c422286d62 Alexandru Ardelean 2024-08-19 830
09d11fa081ef17 Alexandru Ardelean 2024-08-19 831 ret = st->bops->sw_mode_config(indio_dev);
94168a5789874a Alexandru Ardelean 2024-08-19 832 break;
94168a5789874a Alexandru Ardelean 2024-08-19 833 }
09d11fa081ef17 Alexandru Ardelean 2024-08-19 834
09d11fa081ef17 Alexandru Ardelean 2024-08-19 835 for (ch = 0; ch < num_channels; ch++) {
09d11fa081ef17 Alexandru Ardelean 2024-08-19 836 struct ad7606_chan_scale *cs;
09d11fa081ef17 Alexandru Ardelean 2024-08-19 837 int i;
09d11fa081ef17 Alexandru Ardelean 2024-08-19 838
09d11fa081ef17 Alexandru Ardelean 2024-08-19 839 /* AD7606C supports different scales per channel */
09d11fa081ef17 Alexandru Ardelean 2024-08-19 840 cs = &st->chan_scales[ch];
09d11fa081ef17 Alexandru Ardelean 2024-08-19 841
09d11fa081ef17 Alexandru Ardelean 2024-08-19 842 if (num_scales_avail_show == 1 && ch > 0) {
09d11fa081ef17 Alexandru Ardelean 2024-08-19 843 cs->scale_avail_show = scale_avail_show;
09d11fa081ef17 Alexandru Ardelean 2024-08-19 844 continue;
09d11fa081ef17 Alexandru Ardelean 2024-08-19 845 }
09d11fa081ef17 Alexandru Ardelean 2024-08-19 846
09d11fa081ef17 Alexandru Ardelean 2024-08-19 847 scale_avail_show = devm_kcalloc(st->dev, cs->num_scales * 2,
09d11fa081ef17 Alexandru Ardelean 2024-08-19 848 sizeof(*scale_avail_show),
09d11fa081ef17 Alexandru Ardelean 2024-08-19 849 GFP_KERNEL);
09d11fa081ef17 Alexandru Ardelean 2024-08-19 850 if (!scale_avail_show)
09d11fa081ef17 Alexandru Ardelean 2024-08-19 851 return -ENOMEM;
09d11fa081ef17 Alexandru Ardelean 2024-08-19 852
09d11fa081ef17 Alexandru Ardelean 2024-08-19 853 /* Generate a scale_avail list for showing to userspace */
09d11fa081ef17 Alexandru Ardelean 2024-08-19 854 for (i = 0; i < cs->num_scales; i++) {
09d11fa081ef17 Alexandru Ardelean 2024-08-19 855 scale_avail_show[i * 2] = 0;
09d11fa081ef17 Alexandru Ardelean 2024-08-19 856 scale_avail_show[i * 2 + 1] = cs->scale_avail[i];
09d11fa081ef17 Alexandru Ardelean 2024-08-19 857 }
09d11fa081ef17 Alexandru Ardelean 2024-08-19 858
09d11fa081ef17 Alexandru Ardelean 2024-08-19 859 cs->scale_avail_show = scale_avail_show;
09d11fa081ef17 Alexandru Ardelean 2024-08-19 860 }
09d11fa081ef17 Alexandru Ardelean 2024-08-19 861
09d11fa081ef17 Alexandru Ardelean 2024-08-19 862 return 0;
b5d2c422286d62 Alexandru Ardelean 2024-08-19 863 }
b5d2c422286d62 Alexandru Ardelean 2024-08-19 864
On 8/19/24 1:47 AM, Alexandru Ardelean wrote: > The AD7606C-16 and AD7606C-18 are pretty similar with the AD7606B. > The main difference between AD7606C-16 & AD7606C-18 is the precision in > bits (16 vs 18). > Because of that, some scales need to be defined for the 18-bit variants, as > they need to be computed against 2**18 (vs 2**16 for the 16 bit-variants). > > Because the AD7606C-16,18 also supports bipolar & differential channels, > for SW-mode, the default range of 10 V or ±10V should be set at probe. > On reset, the default range (in the registers) is set to value 0x3 which > corresponds to '±10 V single-ended range', regardless of bipolar or > differential configuration. > > Aside from the scale/ranges, the AD7606C-16 is similar to the AD7606B. > > And the AD7606C-18 variant offers 18-bit precision. The unfortunate effect > of this 18-bit sample size, is that there is no simple/neat way to get the > samples into a 32-bit array without having to do a home-brewed bit-buffer. > The ADC must read all samples (from all 8 channels) in order to get the > N-th sample (this could be reworked to do up-to-N-th sample for scan-direct). > There doesn't seem to be any quick-trick to be usable to pad the samples > up to at least 24 bits. > Even the optional status-header is 8-bits, which would mean 26-bits of data > per sample. > That means that when using a simple SPI controller (which can usually read > 8 bit multiples) a simple bit-buffer trick is required. > Maybe it would be better to just use .bits_per_word = 18 for the 18-bit ADC and not worry about "simple" SPI controller support for that one?
On Mon, Aug 19, 2024 at 6:33 PM David Lechner <dlechner@baylibre.com> wrote: > > On 8/19/24 1:47 AM, Alexandru Ardelean wrote: > > The AD7606C-16 and AD7606C-18 are pretty similar with the AD7606B. > > The main difference between AD7606C-16 & AD7606C-18 is the precision in > > bits (16 vs 18). > > Because of that, some scales need to be defined for the 18-bit variants, as > > they need to be computed against 2**18 (vs 2**16 for the 16 bit-variants). > > > > Because the AD7606C-16,18 also supports bipolar & differential channels, > > for SW-mode, the default range of 10 V or ±10V should be set at probe. > > On reset, the default range (in the registers) is set to value 0x3 which > > corresponds to '±10 V single-ended range', regardless of bipolar or > > differential configuration. > > > > Aside from the scale/ranges, the AD7606C-16 is similar to the AD7606B. > > > > And the AD7606C-18 variant offers 18-bit precision. The unfortunate effect > > of this 18-bit sample size, is that there is no simple/neat way to get the > > samples into a 32-bit array without having to do a home-brewed bit-buffer. > > The ADC must read all samples (from all 8 channels) in order to get the > > N-th sample (this could be reworked to do up-to-N-th sample for scan-direct). > > There doesn't seem to be any quick-trick to be usable to pad the samples > > up to at least 24 bits. > > Even the optional status-header is 8-bits, which would mean 26-bits of data > > per sample. > > That means that when using a simple SPI controller (which can usually read > > 8 bit multiples) a simple bit-buffer trick is required. > > > Maybe it would be better to just use .bits_per_word = 18 for the 18-bit > ADC and not worry about "simple" SPI controller support for that one? > +cc Mark Brown for some input on the SPI stuff I'm generally fine with choosing to not support SPI controllers that can't do padding to 16/32 bit arrays But, at the same time: would it be an interesting topic to implement (in the SPI framework) some SW implementation for padding a series of 18-bit samples to 32-bit arrays? (Similarly, this could work for 10-15 bit samples into 16 bit arrays). Apologies if this is already implemented and I missed it. But if there isn't such a functionality (padding done in SW inside the SPI framework), then I could probably spin-up a proposal. I think that the functionality could be spun-up in a separate patch-set/discussion; and this patchset would just go with "bits_per_word = 18". It could be done as a new field in the "struct spi_transfer", or something else like "spi_pad_rx_to_nbits(struct spi_device *)" Or other suggestions welcome Thanks Alex
On 8/23/24 10:54 AM, Alexandru Ardelean wrote: > On Mon, Aug 19, 2024 at 6:33 PM David Lechner <dlechner@baylibre.com> wrote: >> >> On 8/19/24 1:47 AM, Alexandru Ardelean wrote: >>> The AD7606C-16 and AD7606C-18 are pretty similar with the AD7606B. >>> The main difference between AD7606C-16 & AD7606C-18 is the precision in >>> bits (16 vs 18). >>> Because of that, some scales need to be defined for the 18-bit variants, as >>> they need to be computed against 2**18 (vs 2**16 for the 16 bit-variants). >>> >>> Because the AD7606C-16,18 also supports bipolar & differential channels, >>> for SW-mode, the default range of 10 V or ±10V should be set at probe. >>> On reset, the default range (in the registers) is set to value 0x3 which >>> corresponds to '±10 V single-ended range', regardless of bipolar or >>> differential configuration. >>> >>> Aside from the scale/ranges, the AD7606C-16 is similar to the AD7606B. >>> >>> And the AD7606C-18 variant offers 18-bit precision. The unfortunate effect >>> of this 18-bit sample size, is that there is no simple/neat way to get the >>> samples into a 32-bit array without having to do a home-brewed bit-buffer. >>> The ADC must read all samples (from all 8 channels) in order to get the >>> N-th sample (this could be reworked to do up-to-N-th sample for scan-direct). >>> There doesn't seem to be any quick-trick to be usable to pad the samples >>> up to at least 24 bits. >>> Even the optional status-header is 8-bits, which would mean 26-bits of data >>> per sample. >>> That means that when using a simple SPI controller (which can usually read >>> 8 bit multiples) a simple bit-buffer trick is required. >>> >> Maybe it would be better to just use .bits_per_word = 18 for the 18-bit >> ADC and not worry about "simple" SPI controller support for that one? >> > > +cc Mark Brown for some input on the SPI stuff > > I'm generally fine with choosing to not support SPI controllers that > can't do padding to 16/32 bit arrays > > But, at the same time: would it be an interesting topic to implement > (in the SPI framework) some SW implementation for padding a series of > 18-bit samples to 32-bit arrays? > (Similarly, this could work for 10-15 bit samples into 16 bit arrays). > > Apologies if this is already implemented and I missed it. > > But if there isn't such a functionality (padding done in SW inside the > SPI framework), then I could probably spin-up a proposal. > I think that the functionality could be spun-up in a separate > patch-set/discussion; and this patchset would just go with > "bits_per_word = 18". > > It could be done as a new field in the "struct spi_transfer", or > something else like "spi_pad_rx_to_nbits(struct spi_device *)" > Or other suggestions welcome > > Thanks > Alex Seems like it would be tricky to do something in the core code to emulate "odd" sized words in general since what is permissible likely depends on how the individual peripheral works. For example, total_bits = xfer->bits_per_word * (xfer->len / roundup_pow_of_two(BITS_TO_BYTES(xfer->bits_per_word))) If total_bits % 8 != 0, then there will be extra trailing clock cycles that could be problematic on some peripherals but not others. And there are other incompatibilities to consider, like this could not be used with a peripheral that have the CS_WORD flag set (highly unlikely, but still something to consider if we are integrating this into the core). But if you want to look into it more, another use case for this could be SPI TFT displays. There are a number of these that use 9-bit data words. Right now emulation is handled in the peripheral driver code. For example, see mipi_dbi_spi1e_transfer() and fbtft_write_reg8_bus9().
On Mon, 19 Aug 2024 09:47:17 +0300 Alexandru Ardelean <aardelean@baylibre.com> wrote: > The AD7606C-16 and AD7606C-18 are pretty similar with the AD7606B. > The main difference between AD7606C-16 & AD7606C-18 is the precision in > bits (16 vs 18). > Because of that, some scales need to be defined for the 18-bit variants, as > they need to be computed against 2**18 (vs 2**16 for the 16 bit-variants). > > Because the AD7606C-16,18 also supports bipolar & differential channels, > for SW-mode, the default range of 10 V or ±10V should be set at probe. > On reset, the default range (in the registers) is set to value 0x3 which > corresponds to '±10 V single-ended range', regardless of bipolar or > differential configuration. > > Aside from the scale/ranges, the AD7606C-16 is similar to the AD7606B. > > And the AD7606C-18 variant offers 18-bit precision. The unfortunate effect > of this 18-bit sample size, is that there is no simple/neat way to get the > samples into a 32-bit array without having to do a home-brewed bit-buffer. > The ADC must read all samples (from all 8 channels) in order to get the > N-th sample (this could be reworked to do up-to-N-th sample for scan-direct). > There doesn't seem to be any quick-trick to be usable to pad the samples > up to at least 24 bits. > Even the optional status-header is 8-bits, which would mean 26-bits of data > per sample. > That means that when using a simple SPI controller (which can usually read > 8 bit multiples) a simple bit-buffer trick is required. > > Datasheet links: > https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-16.pdf > https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-18.pdf > > Signed-off-by: Alexandru Ardelean <aardelean@baylibre.com> A few minor things. If we can just start with 18 bit word spi controllers only maybe that's worth doing to make things simpler. > +static int ad7606c_sw_mode_setup_channels(struct iio_dev *indio_dev, > + ad7606c_chan_setup_cb_t chan_setup_cb) > +{ > + unsigned int num_channels = indio_dev->num_channels - 1; > + struct ad7606_state *st = iio_priv(indio_dev); > + bool chan_configured[AD760X_MAX_CHANNELS]; = {}; and drop the memset. > + struct device *dev = st->dev; > + int ret; > + u32 ch; > + > + /* We need to hook this first */ > + ret = st->bops->sw_mode_config(indio_dev); > + if (ret) > + return ret; > + > + indio_dev->info = &ad7606c_info_sw_mode; > + > + memset(chan_configured, 0, sizeof(chan_configured)); > + > + device_for_each_child_node_scoped(dev, child) { > + bool bipolar, differential; > + > + ret = fwnode_property_read_u32(child, "reg", &ch); > + if (ret) > + continue; > + > + if (ch >= num_channels) { > + dev_warn(st->dev, > + "Invalid channel number (ignoring): %d\n", ch); > + continue; > + } > + > + bipolar = fwnode_property_present(child, "bipolar"); > + differential = fwnode_property_present(child, "diff-channel"); > + > + chan_setup_cb(st, ch, bipolar, differential); > + chan_configured[ch] = true; > + } > + > + /* Apply default configuration to unconfigured (via DT) channels */ > + for (ch = 0; ch < num_channels; ch++) { > + struct ad7606_chan_scale *cs; > + unsigned int *scale_avail_show; > + int i; > + > + if (!chan_configured[ch]) > + chan_setup_cb(st, ch, false, false); > + > + /* AD7606C supports different scales per channel */ > + cs = &st->chan_scales[ch]; > + > + scale_avail_show = devm_kcalloc(st->dev, cs->num_scales * 2, > + sizeof(*scale_avail_show), > + GFP_KERNEL); Maybe just make it big enough for worst case and stick it in st always? How big can it get? > + if (!scale_avail_show) > + return -ENOMEM; > + > + /* Generate a scale_avail list for showing to userspace */ > + for (i = 0; i < cs->num_scales; i++) { > + scale_avail_show[i * 2] = 0; > + scale_avail_show[i * 2 + 1] = cs->scale_avail[i]; > + } > + > + cs->scale_avail_show = scale_avail_show; > + } > + > + return 0; > +} > > diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c > index dd0075c97c24..73a7b0007bf8 100644 > --- a/drivers/iio/adc/ad7606_spi.c > +++ b/drivers/iio/adc/ad7606_spi.c > @@ -45,6 +45,8 @@ > > +static int ad7606_spi_read_block18to32(struct device *dev, > + int count, void *buf) > +{ > + struct spi_device *spi = to_spi_device(dev); > + u32 i, bit_buffer, buf_size, bit_buf_size; > + u32 *data = buf; > + u8 *bdata = buf; > + int j, ret; > + > + /** Not kernel doc. /* > + * With the 18 bit ADC variants (here) is that we can't assume that all > + * SPI controllers will pad 18-bit sequences into 32-bit arrays, > + * so we need to do a bit of buffer magic here. > + * Alternatively, we can have a variant of this function that works > + * for SPI controllers that can pad 18-bit samples into 32-bit arrays. > + */ > + > + /* Write 'count' bytes to the right, to not overwrite samples */ > + bdata += count; > + > + /* Read 24 bits only, as we'll only get samples of 18 bits each */ > + buf_size = count * 3; > + ret = spi_read(spi, bdata, buf_size); > + if (ret < 0) { > + dev_err(&spi->dev, "SPI read error\n"); > + return ret; > + } > + > + bit_buffer = 0; > + bit_buf_size = 0; > + for (j = 0, i = 0; i < buf_size; i++) { > + u32 sample; > + > + bit_buffer = (bit_buffer << 8) | bdata[i]; > + bit_buf_size += 8; > + > + if (bit_buf_size < 18) > + continue; > + > + bit_buf_size -= 18; > + sample = (bit_buffer >> bit_buf_size) & AD7606C_18_SAMPLE_MASK; > + data[j++] = sign_extend32(sample, 17); > + > + if (j == count) > + break; > + } > + > + return 0; > +}
On Fri, Aug 23, 2024 at 10:19 PM Jonathan Cameron <jic23@kernel.org> wrote: > > On Mon, 19 Aug 2024 09:47:17 +0300 > Alexandru Ardelean <aardelean@baylibre.com> wrote: > > > The AD7606C-16 and AD7606C-18 are pretty similar with the AD7606B. > > The main difference between AD7606C-16 & AD7606C-18 is the precision in > > bits (16 vs 18). > > Because of that, some scales need to be defined for the 18-bit variants, as > > they need to be computed against 2**18 (vs 2**16 for the 16 bit-variants). > > > > Because the AD7606C-16,18 also supports bipolar & differential channels, > > for SW-mode, the default range of 10 V or ±10V should be set at probe. > > On reset, the default range (in the registers) is set to value 0x3 which > > corresponds to '±10 V single-ended range', regardless of bipolar or > > differential configuration. > > > > Aside from the scale/ranges, the AD7606C-16 is similar to the AD7606B. > > > > And the AD7606C-18 variant offers 18-bit precision. The unfortunate effect > > of this 18-bit sample size, is that there is no simple/neat way to get the > > samples into a 32-bit array without having to do a home-brewed bit-buffer. > > The ADC must read all samples (from all 8 channels) in order to get the > > N-th sample (this could be reworked to do up-to-N-th sample for scan-direct). > > There doesn't seem to be any quick-trick to be usable to pad the samples > > up to at least 24 bits. > > Even the optional status-header is 8-bits, which would mean 26-bits of data > > per sample. > > That means that when using a simple SPI controller (which can usually read > > 8 bit multiples) a simple bit-buffer trick is required. > > > > Datasheet links: > > https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-16.pdf > > https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-18.pdf > > > > Signed-off-by: Alexandru Ardelean <aardelean@baylibre.com> > > A few minor things. If we can just start with 18 bit word spi controllers only > maybe that's worth doing to make things simpler. Will go for 18 bit word SPI controllers-only for now. > > > +static int ad7606c_sw_mode_setup_channels(struct iio_dev *indio_dev, > > + ad7606c_chan_setup_cb_t chan_setup_cb) > > +{ > > + unsigned int num_channels = indio_dev->num_channels - 1; > > + struct ad7606_state *st = iio_priv(indio_dev); > > + bool chan_configured[AD760X_MAX_CHANNELS]; > = {}; > and drop the memset. ack > > > + struct device *dev = st->dev; > > + int ret; > > + u32 ch; > > + > > + /* We need to hook this first */ > > + ret = st->bops->sw_mode_config(indio_dev); > > + if (ret) > > + return ret; > > + > > + indio_dev->info = &ad7606c_info_sw_mode; > > + > > + memset(chan_configured, 0, sizeof(chan_configured)); > > + > > + device_for_each_child_node_scoped(dev, child) { > > + bool bipolar, differential; > > + > > + ret = fwnode_property_read_u32(child, "reg", &ch); > > + if (ret) > > + continue; > > + > > + if (ch >= num_channels) { > > + dev_warn(st->dev, > > + "Invalid channel number (ignoring): %d\n", ch); > > + continue; > > + } > > + > > + bipolar = fwnode_property_present(child, "bipolar"); > > + differential = fwnode_property_present(child, "diff-channel"); > > + > > + chan_setup_cb(st, ch, bipolar, differential); > > + chan_configured[ch] = true; > > + } > > + > > + /* Apply default configuration to unconfigured (via DT) channels */ > > + for (ch = 0; ch < num_channels; ch++) { > > + struct ad7606_chan_scale *cs; > > + unsigned int *scale_avail_show; > > + int i; > > + > > + if (!chan_configured[ch]) > > + chan_setup_cb(st, ch, false, false); > > + > > + /* AD7606C supports different scales per channel */ > > + cs = &st->chan_scales[ch]; > > + > > + scale_avail_show = devm_kcalloc(st->dev, cs->num_scales * 2, > > + sizeof(*scale_avail_show), > > + GFP_KERNEL); > > Maybe just make it big enough for worst case and stick it in st always? > How big can it get? So, that would be 16 channels x 8 bytes-per-scale x 5 = 640 bytes. Not too bad. > > > > > + if (!scale_avail_show) > > + return -ENOMEM; > > + > > + /* Generate a scale_avail list for showing to userspace */ > > + for (i = 0; i < cs->num_scales; i++) { > > + scale_avail_show[i * 2] = 0; > > + scale_avail_show[i * 2 + 1] = cs->scale_avail[i]; > > + } > > + > > + cs->scale_avail_show = scale_avail_show; > > + } > > + > > + return 0; > > +} > > > > > diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c > > index dd0075c97c24..73a7b0007bf8 100644 > > --- a/drivers/iio/adc/ad7606_spi.c > > +++ b/drivers/iio/adc/ad7606_spi.c > > @@ -45,6 +45,8 @@ > > > > > +static int ad7606_spi_read_block18to32(struct device *dev, > > + int count, void *buf) > > +{ > > + struct spi_device *spi = to_spi_device(dev); > > + u32 i, bit_buffer, buf_size, bit_buf_size; > > + u32 *data = buf; > > + u8 *bdata = buf; > > + int j, ret; > > + > > + /** > Not kernel doc. /* > > + * With the 18 bit ADC variants (here) is that we can't assume that all > > + * SPI controllers will pad 18-bit sequences into 32-bit arrays, > > + * so we need to do a bit of buffer magic here. > > + * Alternatively, we can have a variant of this function that works > > + * for SPI controllers that can pad 18-bit samples into 32-bit arrays. > > + */ > > + > > + /* Write 'count' bytes to the right, to not overwrite samples */ > > + bdata += count; > > + > > + /* Read 24 bits only, as we'll only get samples of 18 bits each */ > > + buf_size = count * 3; > > + ret = spi_read(spi, bdata, buf_size); > > + if (ret < 0) { > > + dev_err(&spi->dev, "SPI read error\n"); > > + return ret; > > + } > > + > > + bit_buffer = 0; > > + bit_buf_size = 0; > > + for (j = 0, i = 0; i < buf_size; i++) { > > + u32 sample; > > + > > + bit_buffer = (bit_buffer << 8) | bdata[i]; > > + bit_buf_size += 8; > > + > > + if (bit_buf_size < 18) > > + continue; > > + > > + bit_buf_size -= 18; > > + sample = (bit_buffer >> bit_buf_size) & AD7606C_18_SAMPLE_MASK; > > + data[j++] = sign_extend32(sample, 17); > > + > > + if (j == count) > > + break; > > + } > > + > > + return 0; > > +} >
diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 7533aab4b7c8..55faab321092 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -28,14 +28,44 @@ #include "ad7606.h" +typedef void (*ad7606c_chan_setup_cb_t)(struct ad7606_state *st, int ch, + bool bipolar, bool differential); + /* * Scales are computed as 5000/32768 and 10000/32768 respectively, * so that when applied to the raw values they provide mV values */ -static const unsigned int ad7606_scale_avail[2] = { +static const unsigned int ad7606_16bit_hw_scale_avail[2] = { 152588, 305176 }; +static const unsigned int ad7606_18bit_hw_scale_avail[2] = { + 38147, 76294 +}; + +static const unsigned int ad7606c_16_scale_single_ended_unipolar_avail[3] = { + 76294, 152588, 190735, +}; + +static const unsigned int ad7606c_16_scale_single_ended_bipolar_avail[5] = { + 76294, 152588, 190735, 305176, 381470 +}; + +static const unsigned int ad7606c_16_scale_differential_bipolar_avail[4] = { + 152588, 305176, 381470, 610352 +}; + +static const unsigned int ad7606c_18_scale_single_ended_unipolar_avail[3] = { + 19073, 38147, 47684 +}; + +static const unsigned int ad7606c_18_scale_single_ended_bipolar_avail[5] = { + 19073, 38147, 47684, 76294, 95367 +}; + +static const unsigned int ad7606c_18_scale_differential_bipolar_avail[4] = { + 38147, 76294, 95367, 152588 +}; static const unsigned int ad7616_sw_scale_avail[3] = { 76293, 152588, 305176 @@ -84,10 +114,18 @@ static int ad7606_reg_access(struct iio_dev *indio_dev, static int ad7606_read_samples(struct ad7606_state *st) { + unsigned int storagebits = st->chip_info->channels[1].scan_type.storagebits; unsigned int num = st->chip_info->num_channels - 1; - u16 *data = st->data; + u32 *data32 = st->data.d32; + u16 *data16 = st->data.d16; + void *data; int ret; + if (storagebits > 16) + data = data32; + else + data = data16; + /* * The frstdata signal is set to high while and after reading the sample * of the first channel and low for all other channels. This can be used @@ -108,7 +146,10 @@ static int ad7606_read_samples(struct ad7606_state *st) return -EIO; } - data++; + if (storagebits > 16) + data32++; + else + data16++; num--; } @@ -128,7 +169,7 @@ static irqreturn_t ad7606_trigger_handler(int irq, void *p) if (ret) goto error_ret; - iio_push_to_buffers_with_timestamp(indio_dev, st->data, + iio_push_to_buffers_with_timestamp(indio_dev, st->data.d16, iio_get_time_ns(indio_dev)); error_ret: iio_trigger_notify_done(indio_dev->trig); @@ -142,6 +183,7 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, int *val) { struct ad7606_state *st = iio_priv(indio_dev); + unsigned int storagebits = st->chip_info->channels[1].scan_type.storagebits; int ret; gpiod_set_value(st->gpio_convst, 1); @@ -153,8 +195,12 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, } ret = ad7606_read_samples(st); - if (ret == 0) - *val = sign_extend32(st->data[ch], 15); + if (ret == 0) { + if (storagebits > 16) + *val = sign_extend32(st->data.d32[ch], 17); + else + *val = sign_extend32(st->data.d16[ch], 15); + } error_ret: gpiod_set_value(st->gpio_convst, 0); @@ -267,7 +313,7 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, ch = chan->address; cs = &st->chan_scales[ch]; i = find_closest(val2, cs->scale_avail, cs->num_scales); - ret = st->write_scale(indio_dev, ch, i); + ret = st->write_scale(indio_dev, ch, i + cs->reg_offset); if (ret < 0) return ret; cs->range = i; @@ -350,6 +396,18 @@ static const struct iio_chan_spec ad7606_channels_16bit[] = { AD7606_CHANNEL(7, 16), }; +static const struct iio_chan_spec ad7606_channels_18bit[] = { + IIO_CHAN_SOFT_TIMESTAMP(8), + AD7606_CHANNEL(0, 18), + AD7606_CHANNEL(1, 18), + AD7606_CHANNEL(2, 18), + AD7606_CHANNEL(3, 18), + AD7606_CHANNEL(4, 18), + AD7606_CHANNEL(5, 18), + AD7606_CHANNEL(6, 18), + AD7606_CHANNEL(7, 18), +}; + /* * The current assumption that this driver makes for AD7616, is that it's * working in Hardware Mode with Serial, Burst and Sequencer modes activated. @@ -410,6 +468,18 @@ static const struct ad7606_chip_info ad7606_chip_info_tbl[] = { .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), }, + [ID_AD7606C_16] = { + .channels = ad7606_channels_16bit, + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + }, + [ID_AD7606C_18] = { + .channels = ad7606_channels_18bit, + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + }, [ID_AD7616] = { .channels = ad7616_channels, .num_channels = 17, @@ -563,6 +633,14 @@ static const struct iio_info ad7606_info_sw_mode = { .validate_trigger = &ad7606_validate_trigger, }; +static const struct iio_info ad7606c_info_sw_mode = { + .read_raw = &ad7606_read_raw, + .write_raw = &ad7606_write_raw, + .read_avail = &ad7606_read_avail, + .debugfs_reg_access = &ad7606_reg_access, + .validate_trigger = &ad7606_validate_trigger, +}; + static const struct iio_info ad7606_info_os = { .read_raw = &ad7606_read_raw, .write_raw = &ad7606_write_raw, @@ -581,7 +659,136 @@ static const struct iio_trigger_ops ad7606_trigger_ops = { .validate_device = iio_trigger_validate_own_device, }; -static int ad7606_sw_mode_setup(struct iio_dev *indio_dev) +static void ad7606c_18_chan_setup(struct ad7606_state *st, int ch, + bool bipolar, bool differential) +{ + struct ad7606_chan_scale *cs = &st->chan_scales[ch]; + + if (differential) { + cs->scale_avail = + ad7606c_18_scale_differential_bipolar_avail; + cs->num_scales = + ARRAY_SIZE(ad7606c_18_scale_differential_bipolar_avail); + /* Bipolar differential ranges start at 8 (b1000) */ + cs->reg_offset = 8; + cs->range = 1; + } else if (bipolar) { + cs->scale_avail = + ad7606c_18_scale_single_ended_bipolar_avail; + cs->num_scales = + ARRAY_SIZE(ad7606c_18_scale_single_ended_bipolar_avail); + cs->range = 3; + } else { + cs->scale_avail = + ad7606c_18_scale_single_ended_unipolar_avail; + cs->num_scales = + ARRAY_SIZE(ad7606c_18_scale_single_ended_unipolar_avail); + /* Unipolar single-ended ranges start at 5 (b0101) */ + cs->reg_offset = 5; + cs->range = 1; + } +} + +static void ad7606c_16_chan_setup(struct ad7606_state *st, int ch, + bool bipolar, bool differential) +{ + struct ad7606_chan_scale *cs = &st->chan_scales[ch]; + + if (differential) { + cs->scale_avail = + ad7606c_16_scale_differential_bipolar_avail; + cs->num_scales = + ARRAY_SIZE(ad7606c_16_scale_differential_bipolar_avail); + /* Bipolar differential ranges start at 8 (b1000) */ + cs->reg_offset = 8; + cs->range = 1; + } else if (bipolar) { + cs->scale_avail = + ad7606c_16_scale_single_ended_bipolar_avail; + cs->num_scales = + ARRAY_SIZE(ad7606c_16_scale_single_ended_bipolar_avail); + cs->range = 3; + } else { + cs->scale_avail = + ad7606c_16_scale_single_ended_unipolar_avail; + cs->num_scales = + ARRAY_SIZE(ad7606c_16_scale_single_ended_unipolar_avail); + /* Unipolar single-ended ranges start at 5 (b0101) */ + cs->reg_offset = 5; + cs->range = 1; + } +} + +static int ad7606c_sw_mode_setup_channels(struct iio_dev *indio_dev, + ad7606c_chan_setup_cb_t chan_setup_cb) +{ + unsigned int num_channels = indio_dev->num_channels - 1; + struct ad7606_state *st = iio_priv(indio_dev); + bool chan_configured[AD760X_MAX_CHANNELS]; + struct device *dev = st->dev; + int ret; + u32 ch; + + /* We need to hook this first */ + ret = st->bops->sw_mode_config(indio_dev); + if (ret) + return ret; + + indio_dev->info = &ad7606c_info_sw_mode; + + memset(chan_configured, 0, sizeof(chan_configured)); + + device_for_each_child_node_scoped(dev, child) { + bool bipolar, differential; + + ret = fwnode_property_read_u32(child, "reg", &ch); + if (ret) + continue; + + if (ch >= num_channels) { + dev_warn(st->dev, + "Invalid channel number (ignoring): %d\n", ch); + continue; + } + + bipolar = fwnode_property_present(child, "bipolar"); + differential = fwnode_property_present(child, "diff-channel"); + + chan_setup_cb(st, ch, bipolar, differential); + chan_configured[ch] = true; + } + + /* Apply default configuration to unconfigured (via DT) channels */ + for (ch = 0; ch < num_channels; ch++) { + struct ad7606_chan_scale *cs; + unsigned int *scale_avail_show; + int i; + + if (!chan_configured[ch]) + chan_setup_cb(st, ch, false, false); + + /* AD7606C supports different scales per channel */ + cs = &st->chan_scales[ch]; + + scale_avail_show = devm_kcalloc(st->dev, cs->num_scales * 2, + sizeof(*scale_avail_show), + GFP_KERNEL); + if (!scale_avail_show) + return -ENOMEM; + + /* Generate a scale_avail list for showing to userspace */ + for (i = 0; i < cs->num_scales; i++) { + scale_avail_show[i * 2] = 0; + scale_avail_show[i * 2 + 1] = cs->scale_avail[i]; + } + + cs->scale_avail_show = scale_avail_show; + } + + return 0; +} + +static int ad7606_sw_mode_setup(struct iio_dev *indio_dev, unsigned int id) { unsigned int num_channels = indio_dev->num_channels - 1; struct ad7606_state *st = iio_priv(indio_dev); @@ -597,21 +804,33 @@ static int ad7606_sw_mode_setup(struct iio_dev *indio_dev) indio_dev->info = &ad7606_info_sw_mode; - /* Scale of 0.076293 is only available in sw mode */ - /* After reset, in software mode, ±10 V is set by default */ - for (ch = 0; ch < num_channels; ch++) { - struct ad7606_chan_scale *cs = &st->chan_scales[ch]; + switch (id) { + case ID_AD7606C_18: + num_scales_avail_show = num_channels; + ret = ad7606c_sw_mode_setup_channels(indio_dev, + ad7606c_18_chan_setup); + break; + case ID_AD7606C_16: + num_scales_avail_show = num_channels; + ret = ad7606c_sw_mode_setup_channels(indio_dev, + ad7606c_16_chan_setup); + break; + default: + num_scales_avail_show = 1; - cs->scale_avail = ad7616_sw_scale_avail; - cs->num_scales = ARRAY_SIZE(ad7616_sw_scale_avail); - cs->range = 2; - } + /* Scale of 0.076293 is only available in sw mode */ + /* After reset, in software mode, ±10 V is set by default */ + for (ch = 0; ch < num_channels; ch++) { + struct ad7606_chan_scale *cs = &st->chan_scales[ch]; - ret = st->bops->sw_mode_config(indio_dev); - if (ret) - return ret; + cs->scale_avail = ad7616_sw_scale_avail; + cs->num_scales = ARRAY_SIZE(ad7616_sw_scale_avail); + cs->range = 2; + } - num_scales_avail_show = 1; + ret = st->bops->sw_mode_config(indio_dev); + break; + } for (ch = 0; ch < num_channels; ch++) { struct ad7606_chan_scale *cs; @@ -667,9 +886,16 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, st->oversampling = 1; cs = &st->chan_scales[0]; - cs->range = 0; - cs->scale_avail = ad7606_scale_avail; - cs->num_scales = ARRAY_SIZE(ad7606_scale_avail); + switch (id) { + case ID_AD7606C_18: + cs->scale_avail = ad7606_18bit_hw_scale_avail; + cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); + break; + default: + cs->scale_avail = ad7606_16bit_hw_scale_avail; + cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); + break; + } ret = devm_regulator_get_enable(dev, "avcc"); if (ret) @@ -718,7 +944,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, st->write_scale = ad7606_write_scale_hw; st->write_os = ad7606_write_os_hw; - ret = ad7606_sw_mode_setup(indio_dev); + ret = ad7606_sw_mode_setup(indio_dev, id); if (ret) return ret; diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index d71a843a5de5..fa9305923a72 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -22,7 +22,7 @@ .scan_type = { \ .sign = 's', \ .realbits = (bits), \ - .storagebits = (bits), \ + .storagebits = (bits) > 16 ? 32 : 16, \ .endianness = IIO_CPU, \ }, \ } @@ -45,7 +45,7 @@ .scan_type = { \ .sign = 's', \ .realbits = (bits), \ - .storagebits = (bits), \ + .storagebits = (bits) > 16 ? 32 : 16, \ .endianness = IIO_CPU, \ }, \ } @@ -88,12 +88,15 @@ struct ad7606_chip_info { * such that it can be read via the 'read_avail' hook * @num_scales number of elements stored in the scale_avail array * @range voltage range selection, selects which scale to apply + * @reg_offset offset for the register value, to be applied when + * writing the value of 'range' to the register value */ struct ad7606_chan_scale { const unsigned int *scale_avail; const unsigned int *scale_avail_show; unsigned int num_scales; unsigned int range; + unsigned int reg_offset; }; /** @@ -150,9 +153,13 @@ struct ad7606_state { /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. - * 16 * 16-bit samples + 64-bit timestamp + * 16 * 16-bit samples + 64-bit timestamp - for AD7616 + * 8 * 32-bit samples + 64-bit timestamp - for AD7616C-18 (and similar) */ - unsigned short data[20] __aligned(IIO_DMA_MINALIGN); + union { + unsigned short d16[20]; + unsigned int d32[10]; + } data __aligned(IIO_DMA_MINALIGN); __be16 d16[2]; }; @@ -191,6 +198,8 @@ enum ad7606_supported_device_ids { ID_AD7606_6, ID_AD7606_4, ID_AD7606B, + ID_AD7606C_16, + ID_AD7606C_18, ID_AD7616, }; diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index dd0075c97c24..73a7b0007bf8 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -45,6 +45,8 @@ #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) #define AD7606_OS_MODE 0x08 +#define AD7606C_18_SAMPLE_MASK GENMASK(17, 0) + static const struct iio_chan_spec ad7616_sw_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(16), AD7616_CHANNEL(0), @@ -77,6 +79,18 @@ static const struct iio_chan_spec ad7606b_sw_channels[] = { AD7606_SW_CHANNEL(7, 16), }; +static const struct iio_chan_spec ad7606c_18_sw_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(8), + AD7606_SW_CHANNEL(0, 18), + AD7606_SW_CHANNEL(1, 18), + AD7606_SW_CHANNEL(2, 18), + AD7606_SW_CHANNEL(3, 18), + AD7606_SW_CHANNEL(4, 18), + AD7606_SW_CHANNEL(5, 18), + AD7606_SW_CHANNEL(6, 18), + AD7606_SW_CHANNEL(7, 18), +}; + static const unsigned int ad7606B_oversampling_avail[9] = { 1, 2, 4, 8, 16, 32, 64, 128, 256 }; @@ -120,6 +134,56 @@ static int ad7606_spi_read_block(struct device *dev, return 0; } +static int ad7606_spi_read_block18to32(struct device *dev, + int count, void *buf) +{ + struct spi_device *spi = to_spi_device(dev); + u32 i, bit_buffer, buf_size, bit_buf_size; + u32 *data = buf; + u8 *bdata = buf; + int j, ret; + + /** + * With the 18 bit ADC variants (here) is that we can't assume that all + * SPI controllers will pad 18-bit sequences into 32-bit arrays, + * so we need to do a bit of buffer magic here. + * Alternatively, we can have a variant of this function that works + * for SPI controllers that can pad 18-bit samples into 32-bit arrays. + */ + + /* Write 'count' bytes to the right, to not overwrite samples */ + bdata += count; + + /* Read 24 bits only, as we'll only get samples of 18 bits each */ + buf_size = count * 3; + ret = spi_read(spi, bdata, buf_size); + if (ret < 0) { + dev_err(&spi->dev, "SPI read error\n"); + return ret; + } + + bit_buffer = 0; + bit_buf_size = 0; + for (j = 0, i = 0; i < buf_size; i++) { + u32 sample; + + bit_buffer = (bit_buffer << 8) | bdata[i]; + bit_buf_size += 8; + + if (bit_buf_size < 18) + continue; + + bit_buf_size -= 18; + sample = (bit_buffer >> bit_buf_size) & AD7606C_18_SAMPLE_MASK; + data[j++] = sign_extend32(sample, 17); + + if (j == count) + break; + } + + return 0; +} + static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr) { struct spi_device *spi = to_spi_device(st->dev); @@ -283,6 +347,19 @@ static int ad7606B_sw_mode_config(struct iio_dev *indio_dev) return 0; } +static int ad7606c_18_sw_mode_config(struct iio_dev *indio_dev) +{ + int ret; + + ret = ad7606B_sw_mode_config(indio_dev); + if (ret) + return ret; + + indio_dev->channels = ad7606c_18_sw_channels; + + return 0; +} + static const struct ad7606_bus_ops ad7606_spi_bops = { .read_block = ad7606_spi_read_block, }; @@ -305,6 +382,15 @@ static const struct ad7606_bus_ops ad7606B_spi_bops = { .sw_mode_config = ad7606B_sw_mode_config, }; +static const struct ad7606_bus_ops ad7606c_18_spi_bops = { + .read_block = ad7606_spi_read_block18to32, + .reg_read = ad7606_spi_reg_read, + .reg_write = ad7606_spi_reg_write, + .write_mask = ad7606_spi_write_mask, + .rd_wr_cmd = ad7606B_spi_rd_wr_cmd, + .sw_mode_config = ad7606c_18_sw_mode_config, +}; + static int ad7606_spi_probe(struct spi_device *spi) { const struct spi_device_id *id = spi_get_device_id(spi); @@ -315,8 +401,12 @@ static int ad7606_spi_probe(struct spi_device *spi) bops = &ad7616_spi_bops; break; case ID_AD7606B: + case ID_AD7606C_16: bops = &ad7606B_spi_bops; break; + case ID_AD7606C_18: + bops = &ad7606c_18_spi_bops; + break; default: bops = &ad7606_spi_bops; break; @@ -333,6 +423,8 @@ static const struct spi_device_id ad7606_id_table[] = { { "ad7606-6", ID_AD7606_6 }, { "ad7606-8", ID_AD7606_8 }, { "ad7606b", ID_AD7606B }, + { "ad7606c-16", ID_AD7606C_16 }, + { "ad7606c-18", ID_AD7606C_18 }, { "ad7616", ID_AD7616 }, {} }; @@ -344,6 +436,8 @@ static const struct of_device_id ad7606_of_match[] = { { .compatible = "adi,ad7606-6" }, { .compatible = "adi,ad7606-8" }, { .compatible = "adi,ad7606b" }, + { .compatible = "adi,ad7606c-16" }, + { .compatible = "adi,ad7606c-18" }, { .compatible = "adi,ad7616" }, { }, };
The AD7606C-16 and AD7606C-18 are pretty similar with the AD7606B. The main difference between AD7606C-16 & AD7606C-18 is the precision in bits (16 vs 18). Because of that, some scales need to be defined for the 18-bit variants, as they need to be computed against 2**18 (vs 2**16 for the 16 bit-variants). Because the AD7606C-16,18 also supports bipolar & differential channels, for SW-mode, the default range of 10 V or ±10V should be set at probe. On reset, the default range (in the registers) is set to value 0x3 which corresponds to '±10 V single-ended range', regardless of bipolar or differential configuration. Aside from the scale/ranges, the AD7606C-16 is similar to the AD7606B. And the AD7606C-18 variant offers 18-bit precision. The unfortunate effect of this 18-bit sample size, is that there is no simple/neat way to get the samples into a 32-bit array without having to do a home-brewed bit-buffer. The ADC must read all samples (from all 8 channels) in order to get the N-th sample (this could be reworked to do up-to-N-th sample for scan-direct). There doesn't seem to be any quick-trick to be usable to pad the samples up to at least 24 bits. Even the optional status-header is 8-bits, which would mean 26-bits of data per sample. That means that when using a simple SPI controller (which can usually read 8 bit multiples) a simple bit-buffer trick is required. Datasheet links: https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-16.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606c-18.pdf Signed-off-by: Alexandru Ardelean <aardelean@baylibre.com> --- drivers/iio/adc/ad7606.c | 274 ++++++++++++++++++++++++++++++++--- drivers/iio/adc/ad7606.h | 17 ++- drivers/iio/adc/ad7606_spi.c | 94 ++++++++++++ 3 files changed, 357 insertions(+), 28 deletions(-)