diff mbox series

[4/7] iio: adc: adi-axi-adc: set data format

Message ID 20240923101206.3753-5-antoniu.miclaus@analog.com (mailing list archive)
State Changes Requested
Headers show
Series *** Add support for AD485x DAS Family *** | expand

Commit Message

Antoniu Miclaus Sept. 23, 2024, 10:10 a.m. UTC 
Add support for selecting the data format within the AXI ADC ip.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 drivers/iio/adc/adi-axi-adc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

David Lechner Sept. 26, 2024, 9:08 a.m. UTC | #1 
On Mon, Sep 23, 2024 at 12:16 PM Antoniu Miclaus
<antoniu.miclaus@analog.com> wrote:
>
> Add support for selecting the data format within the AXI ADC ip.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
>  drivers/iio/adc/adi-axi-adc.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c
> index ff48f26e02a3..926a8902c621 100644
> --- a/drivers/iio/adc/adi-axi-adc.c
> +++ b/drivers/iio/adc/adi-axi-adc.c
> @@ -45,6 +45,8 @@
>  #define ADI_AXI_ADC_REG_CTRL                   0x0044
>  #define    ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK   BIT(1)
>
> +#define ADI_AXI_ADC_REG_CNTRL_3                        0x004c
> +
>  #define ADI_AXI_ADC_REG_DRP_STATUS             0x0074
>  #define   ADI_AXI_ADC_DRP_LOCKED               BIT(17)
>
> @@ -271,6 +273,24 @@ static int axi_adc_interface_type_get(struct iio_backend *back,
>         return 0;
>  }
>
> +static int axi_adc_data_size_set(struct iio_backend *back,
> +                                ssize_t size)
> +{
> +       struct adi_axi_adc_state *st = iio_backend_get_priv(back);
> +       unsigned int val;
> +
> +       if (size <= 20)
> +               val = 0;
> +       else if (size <= 24)
> +               val = 1;
> +       else if (size <= 32)
> +               val = 3;
> +       else
> +               return -EINVAL;
> +
> +       return regmap_write(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, val);

http://analogdevicesinc.github.io/hdl/library/axi_ad485x/index.html
says that bit 8 of this register is CRC_EN and bits 7 to 0 are
CUSTOM_CONTROL so we likely need a mask and regmap_write_bits() here.

Also, since the value being written here is CUSTOM_CONTROL, it makes
me wonder if this callback really belongs to adi_axi_adc_generic or if
we need a copy of that specific to the axi_ad485x project to handle
the custom meaning of this value for this family of chips. The
description of CUSTOM_CONTROL in the link is "Select output format
decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer
decode , bit 1 - enables alternate bit polarity decode)." which
doesn't look like what is being done in the function above.

> +}
> +
>  static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back,
>                                                  struct iio_dev *indio_dev)
>  {
> @@ -308,6 +328,7 @@ static const struct iio_backend_ops adi_axi_adc_generic = {
>         .test_pattern_set = axi_adc_test_pattern_set,
>         .chan_status = axi_adc_chan_status,
>         .interface_type_get = axi_adc_interface_type_get,
> +       .data_size_set = axi_adc_data_size_set,
>  };
>
>  static int adi_axi_adc_probe(struct platform_device *pdev)
> --
> 2.46.0
>
diff mbox series

Patch

diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c
index ff48f26e02a3..926a8902c621 100644
--- a/drivers/iio/adc/adi-axi-adc.c
+++ b/drivers/iio/adc/adi-axi-adc.c
@@ -45,6 +45,8 @@ 
 #define ADI_AXI_ADC_REG_CTRL			0x0044
 #define    ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK	BIT(1)
 
+#define ADI_AXI_ADC_REG_CNTRL_3			0x004c
+
 #define ADI_AXI_ADC_REG_DRP_STATUS		0x0074
 #define   ADI_AXI_ADC_DRP_LOCKED		BIT(17)
 
@@ -271,6 +273,24 @@  static int axi_adc_interface_type_get(struct iio_backend *back,
 	return 0;
 }
 
+static int axi_adc_data_size_set(struct iio_backend *back,
+				 ssize_t size)
+{
+	struct adi_axi_adc_state *st = iio_backend_get_priv(back);
+	unsigned int val;
+
+	if (size <= 20)
+		val = 0;
+	else if (size <= 24)
+		val = 1;
+	else if (size <= 32)
+		val = 3;
+	else
+		return -EINVAL;
+
+	return regmap_write(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, val);
+}
+
 static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back,
 						 struct iio_dev *indio_dev)
 {
@@ -308,6 +328,7 @@  static const struct iio_backend_ops adi_axi_adc_generic = {
 	.test_pattern_set = axi_adc_test_pattern_set,
 	.chan_status = axi_adc_chan_status,
 	.interface_type_get = axi_adc_interface_type_get,
+	.data_size_set = axi_adc_data_size_set,
 };
 
 static int adi_axi_adc_probe(struct platform_device *pdev)