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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:25 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 11/22] iio: accel: adxl345: import adxl345 general data Date: Thu, 14 Nov 2024 23:09:51 +0000 Message-Id: <20241114231002.98595-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use struct adxl34x_platform_data from the included public header of the input driver for ADXL34x with the following argumentation for this approach: - The iio driver for the ADXL34x covers features also implemented in the older input driver. The iio driver will implement the same features but can also benefit from including the common header and struct adxl34x_platform_data. Once complete, the input driver could be faded out. - The fields in the input driver are identical to the fields the IIO implementation will need. Including the header over reimplementing, avoids a duplication of almost identical headers in IIO and iio. - The header for the input driver is public. It provides a public interface for adxl34x related implementation and is not private to the input system. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 949847fad2..57ecf33d60 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -16,6 +16,8 @@ #include #include +#include + #include "adxl345.h" /* ADXL345 register map */ @@ -126,10 +128,15 @@ */ #define ADXL34x_FIFO_SIZE 33 +static const struct adxl34x_platform_data adxl345_default_init = { + .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, +}; + struct adxl34x_state { int irq; const struct adxl345_chip_info *info; struct regmap *regmap; + struct adxl34x_platform_data data; /* watermark, fifo_mode, etc */ bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; }; @@ -329,6 +336,7 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, unsigned int data_format_mask = (ADXL345_DATA_FORMAT_RANGE | ADXL345_DATA_FORMAT_FULL_RES | ADXL345_DATA_FORMAT_SELF_TEST); + const struct adxl34x_platform_data *data; int ret; indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); @@ -344,6 +352,16 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, return -ENODEV; st->fifo_delay = fifo_delay_default; + data = dev_get_platdata(dev); + if (!data) { + dev_dbg(dev, "No platform data: Using default initialization\n"); + data = &adxl345_default_init; + } + st->data = *data; + + /* some reasonable pre-initialization */ + st->data.act_axis_control = 0xFF; + st->intio = ADXL345_INT1; indio_dev->name = st->info->name;