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[2a02:8389:41cf:e200:1a49:b63:5213:952a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c8acb85sm13699427f8f.103.2024.12.24.02.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 02:59:58 -0800 (PST) From: Javier Carrasco Date: Tue, 24 Dec 2024 11:59:02 +0100 Subject: [PATCH v2 3/4] iio: light: veml3235: extend regmap to add cache Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-veml3235_scale-v2-3-2e1286846c77@gmail.com> References: <20241224-veml3235_scale-v2-0-2e1286846c77@gmail.com> In-Reply-To: <20241224-veml3235_scale-v2-0-2e1286846c77@gmail.com> To: Matti Vaittinen , Jonathan Cameron , Lars-Peter Clausen Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron , Javier Carrasco X-Mailer: b4 0.15-dev-1b0d6 X-Developer-Signature: v=1; a=ed25519-sha256; t=1735037993; l=2136; i=javier.carrasco.cruz@gmail.com; s=20240312; h=from:subject:message-id; bh=sPLOEksW/AM8olcpcDqn2YYtDWmfEDxZzIdwUjGngkA=; b=exK3Xy2BHvv8Bk682aOGsh4yGrCUrI6eV3/2A2FsaCgJf0znOmiw855uhoIUOA3wWKiZ9iveI 3oeixOuNfg6AFSoBGKVyNQgLjAzkdR4S/qaljhN9VJCjc6Ul/SkdAeC X-Developer-Key: i=javier.carrasco.cruz@gmail.com; a=ed25519; pk=lzSIvIzMz0JhJrzLXI0HAdPwsNPSSmEn6RbS+PTS9aQ= The configuration and ID registers are not volatile and are not affected by read operations (i.e. not precious), making them suitable to be cached in order to reduce the number of accesses to the device. Signed-off-by: Javier Carrasco --- drivers/iio/light/veml3235.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/iio/light/veml3235.c b/drivers/iio/light/veml3235.c index fa5c7e7dfbfaec1b96428612b1dcba91ea51603f..f754980ea156a6e128ff159b816e09099197c5c7 100644 --- a/drivers/iio/light/veml3235.c +++ b/drivers/iio/light/veml3235.c @@ -101,12 +101,43 @@ static const struct iio_chan_spec veml3235_channels[] = { }, }; +static const struct regmap_range veml3235_readable_ranges[] = { + regmap_reg_range(VEML3235_REG_CONF, VEML3235_REG_ID), +}; + +static const struct regmap_access_table veml3235_readable_table = { + .yes_ranges = veml3235_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(veml3235_readable_ranges), +}; + +static const struct regmap_range veml3235_writable_ranges[] = { + regmap_reg_range(VEML3235_REG_CONF, VEML3235_REG_CONF), +}; + +static const struct regmap_access_table veml3235_writable_table = { + .yes_ranges = veml3235_writable_ranges, + .n_yes_ranges = ARRAY_SIZE(veml3235_writable_ranges), +}; + +static const struct regmap_range veml3235_volatile_ranges[] = { + regmap_reg_range(VEML3235_REG_WH_DATA, VEML3235_REG_ALS_DATA), +}; + +static const struct regmap_access_table veml3235_volatile_table = { + .yes_ranges = veml3235_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(veml3235_volatile_ranges), +}; + static const struct regmap_config veml3235_regmap_config = { .name = "veml3235_regmap", .reg_bits = 8, .val_bits = 16, .max_register = VEML3235_REG_ID, .val_format_endian = REGMAP_ENDIAN_LITTLE, + .rd_table = &veml3235_readable_table, + .wr_table = &veml3235_writable_table, + .volatile_table = &veml3235_volatile_table, + .cache_type = REGCACHE_RBTREE, }; static int veml3235_get_it(struct veml3235_data *data, int *val, int *val2)