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[2a02:8389:41cf:e200:ec17:b16a:8f4c:782f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf32221e2sm8299423f8f.36.2025.01.19.09.32.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jan 2025 09:32:03 -0800 (PST) From: Javier Carrasco Date: Sun, 19 Jan 2025 18:31:59 +0100 Subject: [PATCH v2 2/4] iio: light: veml6030: extend regmap to support caching Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250119-veml6030-scale-v2-2-6bfc4062a371@gmail.com> References: <20250119-veml6030-scale-v2-0-6bfc4062a371@gmail.com> In-Reply-To: <20250119-veml6030-scale-v2-0-6bfc4062a371@gmail.com> To: Jonathan Cameron , Lars-Peter Clausen , Rishi Gupta , Matti Vaittinen Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron , Javier Carrasco X-Mailer: b4 0.15-dev-1b0d6 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737307920; l=2224; i=javier.carrasco.cruz@gmail.com; s=20240312; h=from:subject:message-id; bh=bWPm28t2DlwzlWZMqKi/LpXy84GMNqzF/p/UNU+O2CE=; b=dGZnrFw9PVNID3Ut0NS0zSiWFgrq2G+XKoBHVioferc8gK5GN6AeM8cdqhV0Avt3V2wtwi8xP qkQYkPgoRRWAWyiJv1VlAhzr9ZhnM5xknft8GZxN8SAWbVEPMWbRAb/ X-Developer-Key: i=javier.carrasco.cruz@gmail.com; a=ed25519; pk=lzSIvIzMz0JhJrzLXI0HAdPwsNPSSmEn6RbS+PTS9aQ= The configuration registers are not volatile and are not affected by read operations (i.e. not precious), making them suitable to be cached in order to reduce the number of accesses to the device. Add support for caching (RBTREE type). Signed-off-by: Javier Carrasco --- drivers/iio/light/veml6030.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/iio/light/veml6030.c b/drivers/iio/light/veml6030.c index 8e4eb8b0c19276635567d4eed74f4d402c3205fa..3afd4bb1ad53157f7ec63a35f51e5a96f7b019fd 100644 --- a/drivers/iio/light/veml6030.c +++ b/drivers/iio/light/veml6030.c @@ -333,12 +333,43 @@ static const struct iio_chan_spec veml7700_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(VEML6030_SCAN_TIMESTAMP), }; +static const struct regmap_range veml6030_readable_ranges[] = { + regmap_reg_range(VEML6030_REG_ALS_CONF, VEML6030_REG_ALS_INT), +}; + +static const struct regmap_access_table veml6030_readable_table = { + .yes_ranges = veml6030_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(veml6030_readable_ranges), +}; + +static const struct regmap_range veml6030_writable_ranges[] = { + regmap_reg_range(VEML6030_REG_ALS_CONF, VEML6030_REG_ALS_PSM), +}; + +static const struct regmap_access_table veml6030_writable_table = { + .yes_ranges = veml6030_writable_ranges, + .n_yes_ranges = ARRAY_SIZE(veml6030_writable_ranges), +}; + +static const struct regmap_range veml6030_volatile_ranges[] = { + regmap_reg_range(VEML6030_REG_ALS_DATA, VEML6030_REG_WH_DATA), +}; + +static const struct regmap_access_table veml6030_volatile_table = { + .yes_ranges = veml6030_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(veml6030_volatile_ranges), +}; + static const struct regmap_config veml6030_regmap_config = { .name = "veml6030_regmap", .reg_bits = 8, .val_bits = 16, .max_register = VEML6030_REG_ALS_INT, .val_format_endian = REGMAP_ENDIAN_LITTLE, + .rd_table = &veml6030_readable_table, + .wr_table = &veml6030_writable_table, + .volatile_table = &veml6030_volatile_table, + .cache_type = REGCACHE_RBTREE, }; static int veml6030_get_intgrn_tm(struct iio_dev *indio_dev,