From patchwork Fri Feb 12 12:13:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12085211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29736C433E0 for ; Fri, 12 Feb 2021 12:18:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E9BE364E13 for ; Fri, 12 Feb 2021 12:18:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231497AbhBLMSU (ORCPT ); Fri, 12 Feb 2021 07:18:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231422AbhBLMQq (ORCPT ); Fri, 12 Feb 2021 07:16:46 -0500 Received: from mail-qk1-x731.google.com (mail-qk1-x731.google.com [IPv6:2607:f8b0:4864:20::731]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CB03C0613D6; Fri, 12 Feb 2021 04:16:06 -0800 (PST) Received: by mail-qk1-x731.google.com with SMTP id x14so8437463qkm.2; Fri, 12 Feb 2021 04:16:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KZvkUbC0jaPZc3fK3Llp2xZbvyDRW9s72WklMpp5HMc=; b=k+DvrR/i5f5H+MFBcZ32t4Cyd2BSGqHDZsGQA90WNIsEkivE8KSvN7PuZy8jlba3d4 AETSBwZgKxx1RWP82usZHjayWUnTsrQUy9qFLovJhy9TRZFOHdRbJ7wRMSkyufq4vMW+ VzTV/1tTxkuK34av9rl22JT2bs8Zc1CJi2AHlqCwNqu+jh+50KjKaoc2ewOmURD71uC2 GAiZttTdIdDxFw7dB0nOqVn+rvtEbs8LGuvi8nJlsaFrVen74B3WuUrY5BdefvBDKp3w lMJxOBCuVgSm2yWUyQUe87bwhEm2AfbpL5XGiLOi03LhIs1YHvCnbtGHqZCORXKSuDb+ VAYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KZvkUbC0jaPZc3fK3Llp2xZbvyDRW9s72WklMpp5HMc=; b=l4CySSmPXRhL6f0wiAn9FZYporF8wYgAyUfAmi/ncSOXexDITYUkbcP57s6+gE4Y+n 7gZYp8E4u1WolXsNOOGZgUmLaKPU96btzBYHPOx2qyb3OYrbozMAOhqVZVyZl0AoXpT/ jxChdA1AXvCiln+US5LH0u9TJdOmlDj7i5RoVlwDCcAsWTWcqeq3VZYaO6VboHTW03Ty uz6b5AbINA/TCxXAWTOpNlTQFXX3/0g7meVnsXXCgwlF4OPuEiDyjaplGTRQsv28jnMH B6cNPibxwRVSHcpJdEwT/MW2ub8OaFSMUulHnlTj2kCAmWwBHTtASeuSOwPPEhVUObME ryxg== X-Gm-Message-State: AOAM531wEurZVGAiGBvfV2aYubfcXhYjp2/Ux+oM9HK4BNDO0s6YyOd7 rGYjw3VhJ9YEEDYgWaqgan0= X-Google-Smtp-Source: ABdhPJxTvJ8G+zm+TB+EKp/mQWmTij02Pwwew5/FJ0ETSrftYDklmUd500bFqy9sERQYLTrvFqRKRQ== X-Received: by 2002:ae9:e110:: with SMTP id g16mr2400877qkm.19.1613132165387; Fri, 12 Feb 2021 04:16:05 -0800 (PST) Received: from localhost.localdomain ([193.27.12.132]) by smtp.gmail.com with ESMTPSA id y135sm6278534qkb.14.2021.02.12.04.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Feb 2021 04:16:04 -0800 (PST) From: William Breathitt Gray To: jic23@kernel.org Cc: kernel@pengutronix.de, linux-stm32@st-md-mailman.stormreply.com, a.fatoum@pengutronix.de, kamel.bouhara@bootlin.com, gwendal@chromium.org, alexandre.belloni@bootlin.com, david@lechnology.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, syednwaris@gmail.com, patrick.havelange@essensium.com, fabrice.gasnier@st.com, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, o.rempel@pengutronix.de, William Breathitt Gray Subject: [PATCH v8 21/22] counter: 104-quad-8: Replace mutex with spinlock Date: Fri, 12 Feb 2021 21:13:45 +0900 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This patch replaces the mutex I/O lock with a spinlock. This is in preparation for a subsequent patch adding IRQ support for 104-QUAD-8 devices; we can't sleep in an interrupt context, so we'll need to use a spinlock instead. Cc: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- drivers/counter/104-quad-8.c | 90 +++++++++++++++++++++--------------- 1 file changed, 53 insertions(+), 37 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index 41fdbd228be3..2b47f9991acc 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -16,6 +16,7 @@ #include #include #include +#include #define QUAD8_EXTENT 32 @@ -28,6 +29,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses"); /** * struct quad8 - device private data structure + * @lock: synchronization lock to prevent I/O race conditions * @counter: instance of the counter_device * @fck_prescaler: array of filter clock prescaler configurations * @preset: array of preset values @@ -42,7 +44,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses"); * @base: base port address of the device */ struct quad8 { - struct mutex lock; + raw_spinlock_t lock; struct counter_device counter; unsigned int fck_prescaler[QUAD8_NUM_COUNTERS]; unsigned int preset[QUAD8_NUM_COUNTERS]; @@ -123,6 +125,7 @@ static int quad8_count_read(struct counter_device *counter, unsigned int flags; unsigned int borrow; unsigned int carry; + unsigned long irqflags; int i; flags = inb(base_offset + 1); @@ -132,7 +135,7 @@ static int quad8_count_read(struct counter_device *counter, /* Borrow XOR Carry effectively doubles count range */ *val = (unsigned long)(borrow ^ carry) << 24; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer; transfer Counter to Output Latch */ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, @@ -141,7 +144,7 @@ static int quad8_count_read(struct counter_device *counter, for (i = 0; i < 3; i++) *val |= (unsigned long)inb(base_offset) << (8 * i); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -151,13 +154,14 @@ static int quad8_count_write(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const int base_offset = priv->base + 2 * count->id; + unsigned long irqflags; int i; /* Only 24-bit values are supported */ if (val > 0xFFFFFF) return -ERANGE; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer */ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); @@ -182,7 +186,7 @@ static int quad8_count_write(struct counter_device *counter, /* Reset Error flag */ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -200,8 +204,9 @@ static int quad8_function_read(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const int id = count->id; + unsigned long irqflags; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); if (priv->quadrature_mode[id]) switch (priv->quadrature_scale[id]) { @@ -218,7 +223,7 @@ static int quad8_function_read(struct counter_device *counter, else *function = COUNTER_FUNCTION_PULSE_DIRECTION; - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -233,10 +238,11 @@ static int quad8_function_write(struct counter_device *counter, unsigned int *const scale = priv->quadrature_scale + id; unsigned int *const synchronous_mode = priv->synchronous_mode + id; const int base_offset = priv->base + 2 * id + 1; + unsigned long irqflags; unsigned int mode_cfg; unsigned int idr_cfg; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); mode_cfg = priv->count_mode[id] << 1; idr_cfg = priv->index_polarity[id] << 1; @@ -271,7 +277,7 @@ static int quad8_function_write(struct counter_device *counter, break; default: /* should never reach this path */ - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } } @@ -279,7 +285,7 @@ static int quad8_function_write(struct counter_device *counter, /* Load mode configuration to Counter Mode Register */ outb(QUAD8_CTR_CMR | mode_cfg, base_offset); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -407,9 +413,10 @@ static int quad8_index_polarity_set(struct counter_device *counter, struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id - 16; const int base_offset = priv->base + 2 * channel_id + 1; + unsigned long irqflags; unsigned int idr_cfg = index_polarity << 1; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); idr_cfg |= priv->synchronous_mode[channel_id]; @@ -418,7 +425,7 @@ static int quad8_index_polarity_set(struct counter_device *counter, /* Load Index Control configuration to Index Control Register */ outb(QUAD8_CTR_IDR | idr_cfg, base_offset); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -447,15 +454,16 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id - 16; const int base_offset = priv->base + 2 * channel_id + 1; + unsigned long irqflags; unsigned int idr_cfg = synchronous_mode; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); idr_cfg |= priv->index_polarity[channel_id] << 1; /* Index function must be non-synchronous in non-quadrature mode */ if (synchronous_mode && !priv->quadrature_mode[channel_id]) { - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } @@ -464,7 +472,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, /* Load Index Control configuration to Index Control Register */ outb(QUAD8_CTR_IDR | idr_cfg, base_offset); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -511,6 +519,7 @@ static int quad8_count_mode_write(struct counter_device *counter, unsigned int count_mode; unsigned int mode_cfg; const int base_offset = priv->base + 2 * count->id + 1; + unsigned long irqflags; /* Map Generic Counter count mode to 104-QUAD-8 count mode */ switch (cnt_mode) { @@ -531,7 +540,7 @@ static int quad8_count_mode_write(struct counter_device *counter, return -EINVAL; } - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); priv->count_mode[count->id] = count_mode; @@ -545,7 +554,7 @@ static int quad8_count_mode_write(struct counter_device *counter, /* Load mode configuration to Counter Mode Register */ outb(QUAD8_CTR_CMR | mode_cfg, base_offset); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -565,9 +574,10 @@ static int quad8_count_enable_write(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const int base_offset = priv->base + 2 * count->id; + unsigned long irqflags; unsigned int ior_cfg; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); priv->ab_enable[count->id] = enable; @@ -576,7 +586,7 @@ static int quad8_count_enable_write(struct counter_device *counter, /* Load I/O control configuration */ outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -627,16 +637,17 @@ static int quad8_count_preset_write(struct counter_device *counter, struct counter_count *count, u64 preset) { struct quad8 *const priv = counter->priv; + unsigned long irqflags; /* Only 24-bit values are supported */ if (preset > 0xFFFFFF) return -ERANGE; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); quad8_preset_register_set(priv, count->id, preset); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -645,8 +656,9 @@ static int quad8_count_ceiling_read(struct counter_device *counter, struct counter_count *count, u64 *ceiling) { struct quad8 *const priv = counter->priv; + unsigned long irqflags; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); /* Range Limit and Modulo-N count modes use preset value as ceiling */ switch (priv->count_mode[count->id]) { @@ -660,7 +672,7 @@ static int quad8_count_ceiling_read(struct counter_device *counter, break; } - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -669,23 +681,24 @@ static int quad8_count_ceiling_write(struct counter_device *counter, struct counter_count *count, u64 ceiling) { struct quad8 *const priv = counter->priv; + unsigned long irqflags; /* Only 24-bit values are supported */ if (ceiling > 0xFFFFFF) return -ERANGE; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); /* Range Limit and Modulo-N count modes use preset value as ceiling */ switch (priv->count_mode[count->id]) { case 1: case 3: - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); quad8_preset_register_set(priv, count->id, ceiling); return 0; } - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } @@ -707,12 +720,13 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const int base_offset = priv->base + 2 * count->id + 1; + unsigned long irqflags; unsigned int ior_cfg; /* Preset enable is active low in Input/Output Control register */ preset_enable = !preset_enable; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); priv->preset_enable[count->id] = preset_enable; @@ -721,7 +735,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, /* Load I/O control configuration to Input / Output Control Register */ outb(QUAD8_CTR_IOR | ior_cfg, base_offset); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -732,22 +746,23 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id / 2; + unsigned long irqflags; bool disabled; unsigned int status; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); disabled = !(priv->cable_fault_enable & BIT(channel_id)); if (disabled) { - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } /* Logic 0 = cable fault */ status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); /* Mask respective channel and invert logic */ *cable_fault = !(status & BIT(channel_id)); @@ -773,9 +788,10 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter, { struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id / 2; + unsigned long irqflags; unsigned int cable_fault_enable; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); if (enable) priv->cable_fault_enable |= BIT(channel_id); @@ -787,7 +803,7 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter, outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -810,8 +826,9 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, struct quad8 *const priv = counter->priv; const size_t channel_id = signal->id / 2; const int base_offset = priv->base + 2 * channel_id; + unsigned long irqflags; - mutex_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, irqflags); priv->fck_prescaler[channel_id] = prescaler; @@ -823,7 +840,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, base_offset + 1); - mutex_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, irqflags); return 0; } @@ -992,8 +1009,7 @@ static int quad8_probe(struct device *dev, unsigned int id) priv->counter.priv = priv; priv->base = base[id]; - /* Initialize mutex */ - mutex_init(&priv->lock); + raw_spin_lock_init(&priv->lock); /* Reset all counters and disable interrupt function */ outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);