From patchwork Fri Jun 24 19:44:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anthony Felice X-Patchwork-Id: 9198087 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A66D16075F for ; Fri, 24 Jun 2016 19:46:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 957CC284D1 for ; Fri, 24 Jun 2016 19:46:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 87FD4284D4; Fri, 24 Jun 2016 19:46:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 28652284D1 for ; Fri, 24 Jun 2016 19:46:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751449AbcFXTpb (ORCPT ); Fri, 24 Jun 2016 15:45:31 -0400 Received: from mail-qk0-f169.google.com ([209.85.220.169]:34864 "EHLO mail-qk0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751315AbcFXTpX (ORCPT ); Fri, 24 Jun 2016 15:45:23 -0400 Received: by mail-qk0-f169.google.com with SMTP id c73so158542518qkg.2 for ; Fri, 24 Jun 2016 12:45:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=timesys-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=x3YAvKwwWvfC9ZcdEw67phL6DH/PDgPIdJA+IGCf0rE=; b=yEAgllmgqYSK3FDeaCigHtGzXJ5Bnfv7hTP0VKhbkP3XYUnWZMKRadydxfUQGoC6gF 9PjEj8jHTP7xaIxfHAK1SHVvhpM1uKIGP+YYh4kqhj5onaICrdr+vylU5lPYG4035uGy 39Oh6beBlrSyrBo3VuAXS58Lc7Wio7TR3jmD24o/nc27M5dS64+3WslPwfMJIrxIKiHM jvoGas4AaovOPIK7V2YmVXo7Mr5o5ECp8vT7fMWJQS6vl9JW9JdScnCN4AVSEaaV/4vD Df8eZJKpdg2ZIvFJyJNbieeBE6OjhS3t8DO4PtPVKjGDJAxUpeWlIDz8xvD02kxJ7A8z apxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x3YAvKwwWvfC9ZcdEw67phL6DH/PDgPIdJA+IGCf0rE=; b=UEtWW5gzlbTuvOC2IRJwugNUKIlAac5y3OmfQUtVQtsZJVfZGopUIypAlCXPL+02mR /JjxS1UhF6QwvD8WJCVm+Z+Vy1TwVBG6dua1HV8vh1S3TrjzGJrYxh7RF7d7OPdxOV8j pigj+644P4uS0o7vcp0ujhNOraGdaEx1jXYsbT8GtjG5SCCjTSOr242PW487JqMyrcE2 HpsZoSjb5iFSJmqLuN72JZ3EXG9i6ha/32jhux/aAMMERZHvDbLpHDKkJwyXkQ2LUHIS jntMfFiXk2OSxmcEgldEcagDegYOfcyd9kYFCLQ0uwaH4RFuha2klUfpe14BhriRC4R5 FcoA== X-Gm-Message-State: ALyK8tK2+EJ3vOILjFjAF8Jt9ukLKnr7mIt6wyCY73cVKrk6Gm74nFPRtPj+8x2fFxQwAp/Y X-Received: by 10.200.48.207 with SMTP id w15mr7015001qta.50.1466797522487; Fri, 24 Jun 2016 12:45:22 -0700 (PDT) Received: from tony-Gazelle.timesys.com ([96.94.100.129]) by smtp.gmail.com with ESMTPSA id 132sm2683156qkh.41.2016.06.24.12.45.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Jun 2016 12:45:22 -0700 (PDT) From: Anthony Felice To: dri-devel@lists.freedesktop.org, shawnguo@kernel.org, tony.felice@timesys.com Cc: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, kernel@pengutronix.de, stefan@agner.ch, linux@armlinux.org.uk, fabio.estevam@nxp.com, geert@linux-m68k.org, mwelling@ieee.org, sre@kernel.org, damien.riegel@savoirfairelinux.com, maitysanchayan@gmail.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/4] ARM: dts: vf610-twr: Enable display controller Date: Fri, 24 Jun 2016 15:44:43 -0400 Message-Id: <1466797486-31558-2-git-send-email-tony.felice@timesys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466797486-31558-1-git-send-email-tony.felice@timesys.com> References: <1466797486-31558-1-git-send-email-tony.felice@timesys.com> Sender: linux-input-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds nodes to enable tcon0 and dcu0 for the Vybrid Tower. These are used to drive the Vybrid Tower TWR-LCD-RGB display. Also, a node for the nec nl4827hc19-05b panel on the TWR-LCD-RGB display has been added. Signed-off-by: Anthony Felice Acked-by: Stefan Agner --- arch/arm/boot/dts/vf610-twr.dts | 48 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index cdc1007..ad1aff9 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -66,6 +66,10 @@ clock-frequency = <50000000>; }; + panel: panel { + compatible = "nec,nl4827hc19-05b"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -134,6 +138,13 @@ <&clks VF610_CLK_ENET_EXT>; }; +&dcu0 { + fsl,panel = <&panel>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dcu0>; + status = "okay"; +}; + &dspi0 { bus-num = <0>; pinctrl-names = "default"; @@ -210,6 +221,39 @@ &iomuxc { vf610-twr { + pinctrl_dcu0: dcu0grp { + fsl,pins = < + VF610_PAD_PTE0__DCU0_HSYNC 0x42 + VF610_PAD_PTE1__DCU0_VSYNC 0x42 + VF610_PAD_PTE2__DCU0_PCLK 0x42 + VF610_PAD_PTE4__DCU0_DE 0x42 + VF610_PAD_PTE5__DCU0_R0 0x42 + VF610_PAD_PTE6__DCU0_R1 0x42 + VF610_PAD_PTE7__DCU0_R2 0x42 + VF610_PAD_PTE8__DCU0_R3 0x42 + VF610_PAD_PTE9__DCU0_R4 0x42 + VF610_PAD_PTE10__DCU0_R5 0x42 + VF610_PAD_PTE11__DCU0_R6 0x42 + VF610_PAD_PTE12__DCU0_R7 0x42 + VF610_PAD_PTE13__DCU0_G0 0x42 + VF610_PAD_PTE14__DCU0_G1 0x42 + VF610_PAD_PTE15__DCU0_G2 0x42 + VF610_PAD_PTE16__DCU0_G3 0x42 + VF610_PAD_PTE17__DCU0_G4 0x42 + VF610_PAD_PTE18__DCU0_G5 0x42 + VF610_PAD_PTE19__DCU0_G6 0x42 + VF610_PAD_PTE20__DCU0_G7 0x42 + VF610_PAD_PTE21__DCU0_B0 0x42 + VF610_PAD_PTE22__DCU0_B1 0x42 + VF610_PAD_PTE23__DCU0_B2 0x42 + VF610_PAD_PTE24__DCU0_B3 0x42 + VF610_PAD_PTE25__DCU0_B4 0x42 + VF610_PAD_PTE26__DCU0_B5 0x42 + VF610_PAD_PTE27__DCU0_B6 0x42 + VF610_PAD_PTE28__DCU0_B7 0x42 + >; + }; + pinctrl_adc0_ad5: adc0ad5grp { fsl,pins = < VF610_PAD_PTC30__ADC0_SE5 0xa1 @@ -370,6 +414,10 @@ status = "okay"; }; +&tcon0 { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>;