From patchwork Thu Dec 26 04:58:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Val Packett X-Patchwork-Id: 13920977 Received: from out-176.mta0.migadu.com (out-176.mta0.migadu.com [91.218.175.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DF47170826 for ; Thu, 26 Dec 2024 05:12:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735189966; cv=none; b=dth74d1HHZYVnb8mtUTPf9JB27NK+bDfc0ivSKgRZiz7TYvDltK/usmmOmtqEfN+rXHQ3xgMm5nE0yxKKfNBWhkTGYTJEg1aNLz04bwxYC9jjPHTXocX0vQnDnhknGsrUfCGSVBK6/WjquThoGN2HYWmI+4shqcNvNc3/kpYU3k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735189966; c=relaxed/simple; bh=+WwSr9Q+JQSUPt+KYRtDM3j/krPJZTfLhQeR5HvDEF4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s+a16dOx8ZpobIaOr3MoFyWeC+T3NUwZFaV5P0TocLT+F5dUiU1fBFi9fz4CGHF/ujjlHwwzrsmDbt+KcyUuecPqf0IXRQTBKQtvfS1lgXg2Qwq4X4aIP4jcSo2T1RQPgI5P1tZbNvtwEzVO2QM4kMZm3XFMkLpX8jqwkGlyvwg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=kM45QCbA; arc=none smtp.client-ip=91.218.175.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="kM45QCbA" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1735189961; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=upNmjojrv0EXOaMqSxtSK3czavePDk/4Zz+86baEfqk=; b=kM45QCbANPdqx+bNe2Sj8x0De/9ILo/3HbUYMOguKQ/xzFsOpqscGERCDU0NZrxoPpw7kC x8mZE29t7nP/CX3vVzk6qQQ0/plDHWQzSCL3niE5IqX7cMPvpZd57UXBMYg6SLOEjCgAm9 ipRuZvojOjXRc6VxAXgl/jOPKIu+yMJdgLPJFXVJbP/MorZtx5JYwl9ZwZxDtSYzfZoBJM VO/twzik51fSWUjCvavzoNjTYMXAjCeKpDNqxKIWHwfEikyiWEZtAjvDoMu+HSVKIeQixS Owu++K2g52JZpd0UqNGDwjEB6Np8phw0CpIOUg06A+LQaDAMNGS7+8cHLGCkgg== From: Val Packett To: Cc: Val Packett , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Eddie Huang , Alexandre Belloni , Javier Carrasco , Fabien Parent , Yassine Oudjana , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-rtc@vger.kernel.org Subject: [PATCH 9/9] arm64: dts: mt6392: add mt6392 PMIC dtsi Date: Thu, 26 Dec 2024 01:58:09 -0300 Message-ID: <20241226050205.30241-10-val@packett.cool> In-Reply-To: <20241226050205.30241-1-val@packett.cool> References: <20241226050205.30241-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT Add the dts to be included by all boards using the MT6392 PMIC. Signed-off-by: Val Packett --- arch/arm64/boot/dts/mediatek/mt6392.dtsi | 232 +++++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6392.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6392.dtsi b/arch/arm64/boot/dts/mediatek/mt6392.dtsi new file mode 100644 index 0000000000000..a7c65dbb043c1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6392.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Copyright (c) 2024 Val Packett + */ + +#include + +&pwrap { + pmic: mt6392 { + compatible = "mediatek,mt6392"; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "mediatek,mt6392-regulator"; + + mt6392_vproc_reg: buck_vproc { + regulator-name = "buck_vproc"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vsys_reg: buck_vsys { + regulator-name = "buck_vsys"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <2987500>; + regulator-ramp-delay = <25000>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vcore_reg: buck_vcore { + regulator-name = "buck_vcore"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vxo22_reg: ldo_vxo22 { + regulator-name = "ldo_vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vaud22_reg: ldo_vaud22 { + regulator-name = "ldo_vaud22"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vcama_reg: ldo_vcama { + regulator-name = "ldo_vcama"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vaud28_reg: ldo_vaud28 { + regulator-name = "ldo_vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vadc18_reg: ldo_vadc18 { + regulator-name = "ldo_vadc18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vcn35_reg: ldo_vcn35 { + regulator-name = "ldo_vcn35"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vio28_reg: ldo_vio28 { + regulator-name = "ldo_vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vusb_reg: ldo_vusb { + regulator-name = "ldo_vusb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vmc_reg: ldo_vmc { + regulator-name = "ldo_vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + regulator-boot-on; + }; + + mt6392_vmch_reg: ldo_vmch { + regulator-name = "ldo_vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + regulator-boot-on; + }; + + mt6392_vemc3v3_reg: ldo_vemc3v3 { + regulator-name = "ldo_vemc3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + regulator-boot-on; + }; + + mt6392_vgp1_reg: ldo_vgp1 { + regulator-name = "ldo_vgp1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vgp2_reg: ldo_vgp2 { + regulator-name = "ldo_vgp2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vcn18_reg: ldo_vcn18 { + regulator-name = "ldo_vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vcamaf_reg: ldo_vcamaf { + regulator-name = "ldo_vcamaf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vm_reg: ldo_vm { + regulator-name = "ldo_vm"; + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1390000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vio18_reg: ldo_vio18 { + regulator-name = "ldo_vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vcamd_reg: ldo_vcamd { + regulator-name = "ldo_vcamd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vcamio_reg: ldo_vcamio { + regulator-name = "ldo_vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6392_vm25_reg: ldo_vm25 { + regulator-name = "ldo_vm25"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + regulator-boot-on; + }; + + mt6392_vefuse_reg: ldo_vefuse { + regulator-name = "ldo_vefuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-enable-ramp-delay = <264>; + }; + }; + + rtc { + compatible = "mediatek,mt6392-rtc"; + }; + + keys { + compatible = "mediatek,mt6392-keys"; + + key-power { + linux,keycodes = ; + wakeup-source; + }; + + key-home { + linux,keycodes = ; + wakeup-source; + }; + }; + }; +};