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Wed, 1 Mar 2023 09:34:00 -0800 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 1 Mar 2023 09:34:00 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.5 via Frontend Transport; Wed, 1 Mar 2023 09:33:56 -0800 From: Krishna Yarlagadda To: , , , , , , , , , CC: , , , , Krishna Yarlagadda Subject: [Patch V7 0/3] Tegra TPM driver with HW flow control Date: Wed, 1 Mar 2023 23:03:50 +0530 Message-ID: <20230301173353.28673-1-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00010206:EE_|DM6PR12MB4402:EE_ X-MS-Office365-Filtering-Correlation-Id: dc5fa5b4-b4f6-41db-a7fa-08db1a7b2ba8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2023 17:34:11.6955 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc5fa5b4-b4f6-41db-a7fa-08db1a7b2ba8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010206.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4402 Precedence: bulk List-ID: X-Mailing-List: linux-integrity@vger.kernel.org TPM devices may insert wait state on last clock cycle of ADDR phase. For SPI controllers that support full-duplex transfers, this can be detected using software by reading the MISO line. For SPI controllers that only support half-duplex transfers, such as the Tegra QSPI, it is not possible to detect the wait signal from software. The QSPI controller in Tegra234 and Tegra241 implement hardware detection of the wait signal which can be enabled in the controller for TPM devices. Add HW flow control in TIS driver and a flag in SPI data to indicate wait detection is required in HW. SPI controller driver determines if this is supported. Add HW detection in Tegra QSPI controller. Updates in this patch set - Tegra QSPI identifies itself as half duplex. - TPM TIS SPI driver skips flow control for half duplex and send transfers in single message for controller to handle it. - TPM device identifies as TPM device for controller to detect and enable HW TPM wait poll feature. Verified with a TPM device on Tegra241 ref board using TPM2 tools. V7: - updated patch description. - TPM flag set in probe. - minor comments. V6: - Fix typo in chip name Tegra234. - Debug logs change skipped to be sent later. - Consistent usage of soc flag. V5: - No SPI bus locking. V4: - Split api change to different patch. - Describe TPM HW flow control. V3: - Use SPI device mode flag and SPI controller flags. - Drop usage of device tree flags. - Generic TPM half duplex controller handling. - HW & SW flow control for TPM. Drop additional driver. V2: - Fix dt schema errors. Krishna Yarlagadda (3): spi: Add TPM HW flow flag tpm_tis-spi: Add hardware wait polling spi: tegra210-quad: Enable TPM wait polling drivers/char/tpm/tpm_tis_spi_main.c | 96 ++++++++++++++++++++++++++++- drivers/spi/spi-tegra210-quad.c | 14 +++++ include/linux/spi/spi.h | 16 ++++- 3 files changed, 121 insertions(+), 5 deletions(-)