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Fri, 3 Feb 2023 05:01:51 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 3 Feb 2023 05:01:50 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 3 Feb 2023 05:01:46 -0800 From: Krishna Yarlagadda To: , , , , , , , , , CC: , , , , Krishna Yarlagadda Subject: [Patch V2 1/4] dt-bindings: tpm: Add compatible for Tegra TPM Date: Fri, 3 Feb 2023 18:31:30 +0530 Message-ID: <20230203130133.32901-2-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230203130133.32901-1-kyarlagadda@nvidia.com> References: <20230203130133.32901-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT085:EE_|CH0PR12MB5187:EE_ X-MS-Office365-Filtering-Correlation-Id: 73317ae1-0ecc-45b9-046f-08db05e6d898 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2023 13:02:03.5952 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73317ae1-0ecc-45b9-046f-08db05e6d898 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5187 Precedence: bulk List-ID: X-Mailing-List: linux-integrity@vger.kernel.org Tegra234 and Tegra241 devices have QSPI controller that supports TPM devices. Since the controller only supports half duplex, sw wait polling method implemented in tpm_tis_spi does not suffice. Wait polling as per protocol is a hardware feature. Add compatible for Tegra TPM driver with hardware flow control. Signed-off-by: Krishna Yarlagadda --- .../security/tpm/nvidia,tegra-tpm-spi.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml diff --git a/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml b/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml new file mode 100644 index 000000000000..dcb78db7355c --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/security/tpm/nvidia,tegra-tpm-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra QSPI TPM driver + +maintainers: + - Thierry Reding + - Jonathan Hunter + +properties: + compatible: + enum: + - nvidia,tegra-tpm-spi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + qspi1@3250000 { + tpm@0 { + compatible = "nvidia,tegra-tpm-spi"; + reg = <0>; + }; + };