| Message ID | 20230223162635.19747-4-kyarlagadda@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Tegra TPM driver with HW flow control | expand |
On Thu, Feb 23, 2023 at 09:56:35PM +0530, Krishna Yarlagadda wrote: > Trusted Platform Module requires flow control. As defined in TPM > interface specification, client would drive MISO line at same cycle as > last address bit on MOSI. > Tegra241 QSPI controller has TPM wait state detection feature which is > enabled for TPM client devices reported in SPI device mode bits. > Set half duplex flag for TPM device to detect and send entire message > to controller in one shot. I don't really understand what the controller is actually doing here, or what the intended effect of the SPI_TPM_HW_FLOW flag is supposed to be. > /* Enable Combined sequence mode */ > val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); > + if (spi->mode & SPI_TPM_HW_FLOW) { > + if (tqspi->soc_data->tpm_wait_poll) > + val |= QSPI_TPM_WAIT_POLL_EN; > + else > + return -EIO; > + } This just sets a bit in a register... > val |= QSPI_CMB_SEQ_EN; > tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); > /* Process individual transfer list */ ...my guess is that setting that bit causes the individual transfers to be delayed in completing without further changes? Is is just some transfers or all of them?
> -----Original Message----- > From: Mark Brown <broonie@kernel.org> > Sent: 23 February 2023 22:59 > To: Krishna Yarlagadda <kyarlagadda@nvidia.com> > Cc: robh+dt@kernel.org; peterhuewe@gmx.de; jgg@ziepe.ca; > jarkko@kernel.org; krzysztof.kozlowski+dt@linaro.org; linux- > spi@vger.kernel.org; linux-tegra@vger.kernel.org; linux- > integrity@vger.kernel.org; linux-kernel@vger.kernel.org; > thierry.reding@gmail.com; Jonathan Hunter <jonathanh@nvidia.com>; > Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan > <ldewangan@nvidia.com> > Subject: Re: [Patch V3 3/3] spi: tegra210-quad: Enable TPM wait polling > > On Thu, Feb 23, 2023 at 09:56:35PM +0530, Krishna Yarlagadda wrote: > > > Trusted Platform Module requires flow control. As defined in TPM > > interface specification, client would drive MISO line at same cycle as > > last address bit on MOSI. > > Tegra241 QSPI controller has TPM wait state detection feature which is > > enabled for TPM client devices reported in SPI device mode bits. > > Set half duplex flag for TPM device to detect and send entire message > > to controller in one shot. > > I don't really understand what the controller is actually doing here, or > what the intended effect of the SPI_TPM_HW_FLOW flag is supposed to be. > > > /* Enable Combined sequence mode */ > > val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); > > + if (spi->mode & SPI_TPM_HW_FLOW) { > > + if (tqspi->soc_data->tpm_wait_poll) > > + val |= QSPI_TPM_WAIT_POLL_EN; > > + else > > + return -EIO; > > + } > > This just sets a bit in a register... > > > val |= QSPI_CMB_SEQ_EN; > > tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); > > /* Process individual transfer list */ > > ...my guess is that setting that bit causes the individual transfers to > be delayed in completing without further changes? Is is just some > transfers or all of them? TPM spec define flow control over SPI. TPM device/client inserts wait state on MISO line when address is transferred on MOSI. This state has to be detected by reading the MISO line which needs full duplex transfer during address phase. Tegra QSPI controller can only support half duplex. But in combined sequence mode, it can detect wait state inserted by TPM device and send or receive data when device is ready. Detection happens on all transfers with TPM.
diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index b967576b6c96..fe15fa6eecd1 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -142,6 +142,7 @@ #define QSPI_GLOBAL_CONFIG 0X1a4 #define QSPI_CMB_SEQ_EN BIT(0) +#define QSPI_TPM_WAIT_POLL_EN BIT(1) #define QSPI_CMB_SEQ_ADDR 0x1a8 #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0) @@ -164,6 +165,7 @@ struct tegra_qspi_soc_data { bool has_dma; bool cmb_xfer_capable; + bool tpm_wait_poll; unsigned int cs_count; }; @@ -991,6 +993,14 @@ static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi) dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS), tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS)); + dev_dbg(tqspi->dev, "GLOBAL_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG)); + dev_dbg(tqspi->dev, "CMB_CMD: 0x%08x | CMB_CMD_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_CMD), + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_CMD_CFG)); + dev_dbg(tqspi->dev, "CMB_ADDR: 0x%08x | CMB_ADDR_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_ADDR), + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_ADDR_CFG)); } static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) @@ -1065,6 +1075,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, /* Enable Combined sequence mode */ val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); + if (spi->mode & SPI_TPM_HW_FLOW) { + if (tqspi->soc_data->tpm_wait_poll) + val |= QSPI_TPM_WAIT_POLL_EN; + else + return -EIO; + } val |= QSPI_CMB_SEQ_EN; tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); /* Process individual transfer list */ @@ -1192,6 +1208,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, /* Disable Combined sequence mode */ val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); val &= ~QSPI_CMB_SEQ_EN; + val &= ~QSPI_TPM_WAIT_POLL_EN; tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); list_for_each_entry(transfer, &msg->transfers, transfer_list) { struct spi_transfer *xfer = transfer; @@ -1450,24 +1467,28 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) static struct tegra_qspi_soc_data tegra210_qspi_soc_data = { .has_dma = true, .cmb_xfer_capable = false, + .tpm_wait_poll = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra186_qspi_soc_data = { .has_dma = true, .cmb_xfer_capable = true, + .tpm_wait_poll = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra234_qspi_soc_data = { .has_dma = false, .cmb_xfer_capable = true, + .tpm_wait_poll = true, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra241_qspi_soc_data = { .has_dma = false, .cmb_xfer_capable = true, + .tpm_wait_poll = true, .cs_count = 4, };
Trusted Platform Module requires flow control. As defined in TPM interface specification, client would drive MISO line at same cycle as last address bit on MOSI. Tegra241 QSPI controller has TPM wait state detection feature which is enabled for TPM client devices reported in SPI device mode bits. Set half duplex flag for TPM device to detect and send entire message to controller in one shot. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> --- drivers/spi/spi-tegra210-quad.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)