From patchwork Tue Sep 12 21:57:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 9950193 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1EBF36038F for ; Tue, 12 Sep 2017 21:58:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1004728CB3 for ; Tue, 12 Sep 2017 21:58:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 046B829029; Tue, 12 Sep 2017 21:58:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 42CB228CB3 for ; Tue, 12 Sep 2017 21:58:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751628AbdILV6A (ORCPT ); Tue, 12 Sep 2017 17:58:00 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:32874 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751519AbdILV5w (ORCPT ); Tue, 12 Sep 2017 17:57:52 -0400 Received: by mail-pg0-f68.google.com with SMTP id i130so4741848pgc.0 for ; Tue, 12 Sep 2017 14:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20150623.gappssmtp.com; s=20150623; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=HqiETOPnlM5Al899qg/LEClsShJuzMsYvcO9tVcJUxE=; b=vCkNT6p8Fd93TqIDv+DdYJ+mK87KRTXFsq2IuB6EAlh6lm5BUpOIz8a84MNWIGN1na 8wtTcD34TtcGOduRGkvCJ5ofJmB9cigmXla6vRh04gKVAG7H+wbiYjCUMNvYL8dsgW8a f0cs9o/IczrX/pQd62ls5rlkVX1z3rxf9IxhtcFlKEyZV/iHO9XFrltlPTXWSB7ZHBLv jbpwl/M7Mhje1KWMc92MitVh7TVukN8URYqtjMWmKmw+A+iQiTd5kbY/nlPt0UVSDsZv +KufigOido8h70LR7BcNn8sNArS/050iBQoPrB3L0lnDgqihXiIrt7pMVOEUAiuz2Q44 M/GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=HqiETOPnlM5Al899qg/LEClsShJuzMsYvcO9tVcJUxE=; b=Wpsuhsnr0yMXRm78bkYhkURg3bJ4V/uGvVr69/NB58idPLYtbu0IdCYS8PeXPVtQYy /Ms7Nyc1AOAipgvLxGhk7dfHZPfJgvod0uR/BE6IKOkhP5063LEmlMmWuVVlt90v/2nx ZQVx2TdYaGYvGAoX+6LxR0emxEkKZlcoiprrA8FGig/4NI4Wppkqg0ccquj+6rKzvMzm VqAKq/KOnSvdUcTDv+ZH1CJAufKmAGctmZyRgrU/Hke4QT5YvGxhBOTKXYX7QYwtq7G2 S4YrHlRU2vMV7b298P0cmR0H5kkKuTlmvz6n0qu5Yz1T4FL0yDMNOg2l9w5B5cERvetP GBwQ== X-Gm-Message-State: AHPjjUjToDkkH9xew3gAVrIdPqkZQakyLEpJJqTM0PpqGr0INi7XN/jJ /nG6aqAHlXeQ3BhQ X-Google-Smtp-Source: ADKCNb4i0/t/VF1vzPjL4MI2MQyqfCLjhiqiz5ZD2uoaj+aMDCguGp6UwGBL6k+fZIA8ns0WDgZ26g== X-Received: by 10.98.178.66 with SMTP id x63mr15828753pfe.332.1505253471226; Tue, 12 Sep 2017 14:57:51 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id q13sm18803500pgt.87.2017.09.12.14.57.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 14:57:50 -0700 (PDT) Subject: [PATCH v8 06/18] clocksource: New RISC-V SBI timer driver Date: Tue, 12 Sep 2017 14:57:03 -0700 Message-Id: <20170912215715.4186-7-palmer@dabbelt.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912215715.4186-1-palmer@dabbelt.com> References: <20170912215715.4186-1-palmer@dabbelt.com> Cc: yamada.masahiro@socionext.com, mmarek@suse.com, albert@sifive.com, will.deacon@arm.com, boqun.feng@gmail.com, oleg@redhat.com, mingo@redhat.com, daniel.lezcano@linaro.org, gregkh@linuxfoundation.org, jslaby@suse.com, davem@davemloft.net, mchehab@kernel.org, hverkuil@xs4all.nl, rdunlap@infradead.org, viro@zeniv.linux.org.uk, mhiramat@kernel.org, fweisbec@gmail.com, mcgrof@kernel.org, dledford@redhat.com, bart.vanassche@sandisk.com, sstabellini@kernel.org, mpe@ellerman.id.au, rmk+kernel@armlinux.org.uk, paul.gortmaker@windriver.com, nicolas.dichtel@6wind.com, linux@roeck-us.net, heiko.carstens@de.ibm.com, schwidefsky@de.ibm.com, geert@linux-m68k.org, akpm@linux-foundation.org, andriy.shevchenko@linux.intel.com, jiri@mellanox.com, vgupta@synopsys.com, airlied@redhat.com, jk@ozlabs.org, chris@chris-wilson.co.uk, Jason@zx2c4.com, paulmck@linux.vnet.ibm.com, ncardwell@google.com, linux-kernel@vger.kernel.org, linux-kbuild@vger.kernel.org, patches@groups.riscv.org, Palmer Dabbelt From: Palmer Dabbelt To: peterz@infradead.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, Arnd Bergmann , dmitriy@oss-tech.org Sender: linux-kbuild-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kbuild@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. This driver attempts to split out the RISC-V ISA specific mechanisms of accessing the hardware from the clocksource driver by taking a pair of function pointers to issue the actual RISC-V specific instructions. Signed-off-by: Dmitriy Cherkasov Signed-off-by: Palmer Dabbelt --- drivers/clocksource/Kconfig | 8 ++++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/riscv_timer.c | 58 +++++++++++++++++++++++++++++++++++++++ include/linux/timer_riscv.h | 34 +++++++++++++++++++++++ 4 files changed, 101 insertions(+) create mode 100644 drivers/clocksource/riscv_timer.c create mode 100644 include/linux/timer_riscv.h diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 54a67f8a28eb..aae9543cef68 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -607,4 +607,12 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. +config RISCV_TIMER + bool "Timer for the RISC-V platform" if COMPILE_TEST + depends on RISCV + help + This enables the per-hart timer built into all RISC-V systems, which + is accessed via both the SBI and the rdcycle instruction. This is + required for all RISC-V systems. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 6df949402dfc..20d75b3f22e4 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -73,3 +73,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o +obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c new file mode 100644 index 000000000000..bbdee730240a --- /dev/null +++ b/drivers/clocksource/riscv_timer.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define MINDELTA 100 +#define MAXDELTA 0x7fffffff + +/* + * See for the rationale behind pre-allocating per-cpu + * timers on RISC-V systems. + */ +DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = { + .name = "riscv_timer_clockevent", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 300, + .set_state_oneshot = NULL, + .set_state_shutdown = NULL, +}; + +static struct clocksource cs = { + .name = "riscv_clocksource", + .rating = 300, + .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void clocksource_riscv_init(unsigned long long (*rdtime)(struct clocksource *)) +{ + cs.read = rdtime; + clocksource_register_hz(&cs, riscv_timebase); +} + +void timer_riscv_init(int cpu_id, + unsigned long riscv_timebase, + int (*next)(unsigned long, struct clock_event_device*)) +{ + struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu_id); + + ce->cpumask = cpumask_of(cpu_id); + ce->set_next_event = next; + + clockevents_config_and_register(ce, riscv_timebase, MINDELTA, MAXDELTA); +} diff --git a/include/linux/timer_riscv.h b/include/linux/timer_riscv.h new file mode 100644 index 000000000000..599358177d1b --- /dev/null +++ b/include/linux/timer_riscv.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2017 SiFive + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LINUX_TIMER_RISCV_H +#define _LINUX_TIMER_RISCV_H + +/* + * All RISC-V systems have a timer attached to every hart. These timers can be + * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup + * events. In order to abstract the architecture-specific timer reading and + * setting functions away from the clock event insertion code, we provide + * function pointers to the clockevent subsystem that perform two basic operations: + * rdtime() reads the timer on the current CPU, and next_event(delta) sets the + * next timer event to 'delta' cycles in the future. As the timers are + * inherently a per-cpu resource, these callbacks perform operations on the + * current hart. There is guaranteed to be exactly one timer per hart on all + * RISC-V systems. + */ +void timer_riscv_init(int cpu_id, + unsigned long riscv_timebase, + int (*next_event)(unsigned long, struct clock_event_device *)); + +void clocksource_riscv_init(unsigned long long (*rdtime)(struct clocksource *)); +#endif