From patchwork Thu Jun 7 18:32:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Desaulniers X-Patchwork-Id: 10453401 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9EDE360467 for ; Thu, 7 Jun 2018 18:33:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8EE82205AF for ; Thu, 7 Jun 2018 18:33:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 81D37228C8; Thu, 7 Jun 2018 18:33:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0D3E205AF for ; Thu, 7 Jun 2018 18:33:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936321AbeFGSco (ORCPT ); Thu, 7 Jun 2018 14:32:44 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:36210 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935086AbeFGScm (ORCPT ); Thu, 7 Jun 2018 14:32:42 -0400 Received: by mail-pg0-f68.google.com with SMTP id m5-v6so5154591pgd.3 for ; Thu, 07 Jun 2018 11:32:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yGeT2z0TEJiRxrbez/GsuqB8RgVtytCBVtTQ7JK4sXk=; b=HEY9qXL0YcX2J/MicPECY+V3ZoGxJP/xLAozSfgprvI3D92IZpm8v4ObDuMESHGzaZ OjxTgmRCC9Zmem1Llyw95kbepoh7KsvzS6MNlWBfgPk1gcn0MQy3nnC1xqtu74v+l2qU IfOsjUYoY/RR7vT641Im4/kZtTR81HpVoaeEoVEV7zWiWDw7hTPmWFpWJnMZmxleJ4S6 200zJnowE8s2fQ/pcvbjKK0LyIBGS3kXaDSMq7bgvSe7/FHc2AlkWds4Sc0+au6/FVz/ CTee8j0BE4xELO9CeEUBqUnprYHSh+Vhr2+xG5OKV1IqAnydbk67U73nsuV+lod5xp26 JbMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yGeT2z0TEJiRxrbez/GsuqB8RgVtytCBVtTQ7JK4sXk=; b=WkuawNUrgPwEHM1xZPs7oFQ39vGt7GZHej3SpBlii6y9M2nKvLLJ1i82NEEns7a3tk 79qrn+r5a9NqpQg0S6riDu1ms5rXpk/PbJPjkd26L7pzimqaDz/zCs9Q5whVTdN9dAvn fo49XAXoYqRi9emPtLv14FpIsf4sPRAtjo96igSkqxMAoj4OJAoypmRHEGYdJeYkq2bO JlNINdxHbaFOhY5CeLugTFcj3eJpNQiBhG5xpvH3qO+Iy/AOflOAcVKnIQpGfNFB8zHl fmxC5rp7d+JG2I0AY/xYHLdAADWTZC+KQgAF2Bv+xNAcWLl0ldjw7TtJiYO7G+arMPwd vKLA== X-Gm-Message-State: APt69E15IuA7tEfLd5Y4EIrLdjquH1rdl7qfQH+jS3wiA69xdudmvHZf DYwoRbSC9EKUHxX2p36U5/GBTg== X-Google-Smtp-Source: ADUXVKIGM8arhElcDh7dZYE268X/tBQJDJ/k5GqXsRFnnWciR39Ccu/nvu8o2N7d99EPc3yHTG8JLw== X-Received: by 2002:a62:418b:: with SMTP id g11-v6mr2801235pfd.51.1528396360716; Thu, 07 Jun 2018 11:32:40 -0700 (PDT) Received: from ndesaulniers0.svl.corp.google.com ([2620:15c:2a3:1:d33:166f:5b79:14b3]) by smtp.gmail.com with ESMTPSA id n76-v6sm6932739pfg.98.2018.06.07.11.32.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Jun 2018 11:32:39 -0700 (PDT) From: Nick Desaulniers To: akpm@linux-foundation.org, hpa@zytor.com, mingo@redhat.com, tglx@linutronix.de Cc: linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, virtualization@lists.linux-foundation.org, astrachan@google.com, manojgupta@google.com, ghackmann@google.com, sedat.dilek@gmail.com, tstellar@redhat.com, keescook@google.com, yamada.masahiro@socionext.com, michal.lkml@markovi.net, linux-kbuild@vger.kernel.org, geert@linux-m68k.org, will.deacon@arm.com, mawilcox@microsoft.com, arnd@arndb.de, rientjes@google.com, acme@redhat.com, pombredanne@nexb.com, aryabinin@virtuozzo.com, kstewart@linuxfoundation.org, boris.ostrovsky@oracle.com, jan.kiszka@siemens.com, rostedt@goodmis.org, kirill.shutemov@linux.intel.com, ard.biesheuvel@linaro.org, akataria@vmware.com, brijesh.singh@amd.com, caoj.fnst@cn.fujitsu.com, gregkh@linuxfoundation.org, jarkko.sakkinen@linux.intel.com, jgross@suse.com, jpoimboe@redhat.com, mka@chromium.org, ndesaulniers@google.com, thomas.lendacky@amd.com, tweek@google.com, mjg59@google.com, joe@perches.com, "H. Peter Anvin" Subject: [PATCH v3 2/3] x86/asm: add _ASM_ARG* constants for argument registers to Date: Thu, 7 Jun 2018 11:32:18 -0700 Message-Id: <20180607183219.192973-3-ndesaulniers@google.com> X-Mailer: git-send-email 2.17.1.1185.g55be947832-goog In-Reply-To: <20180607183219.192973-1-ndesaulniers@google.com> References: <20180607183219.192973-1-ndesaulniers@google.com> Sender: linux-kbuild-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kbuild@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "H. Peter Anvin" i386 and x86-64 uses different registers for arguments; make them available so we don't have to #ifdef in the actual code. Native size and specified size (q, l, w, b) versions are provided. Suggested-by: Sedat Dilek Signed-off-by: H. Peter Anvin Signed-off-by: Nick Desaulniers --- arch/x86/include/asm/asm.h | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h index 219faaec51df..990770f9e76b 100644 --- a/arch/x86/include/asm/asm.h +++ b/arch/x86/include/asm/asm.h @@ -46,6 +46,65 @@ #define _ASM_SI __ASM_REG(si) #define _ASM_DI __ASM_REG(di) +#ifndef __x86_64__ +/* 32 bit */ + +#define _ASM_ARG1 _ASM_AX +#define _ASM_ARG2 _ASM_DX +#define _ASM_ARG3 _ASM_CX + +#define _ASM_ARG1L eax +#define _ASM_ARG2L edx +#define _ASM_ARG3L ecx + +#define _ASM_ARG1W ax +#define _ASM_ARG2W dx +#define _ASM_ARG3W cx + +#define _ASM_ARG1B al +#define _ASM_ARG2B dl +#define _ASM_ARG3B cl + +#else +/* 64 bit */ + +#define _ASM_ARG1 _ASM_DI +#define _ASM_ARG2 _ASM_SI +#define _ASM_ARG3 _ASM_DX +#define _ASM_ARG4 _ASM_CX +#define _ASM_ARG5 r8 +#define _ASM_ARG6 r9 + +#define _ASM_ARG1Q rdi +#define _ASM_ARG2Q rsi +#define _ASM_ARG3Q rdx +#define _ASM_ARG4Q rcx +#define _ASM_ARG5Q r8 +#define _ASM_ARG6Q r9 + +#define _ASM_ARG1L edi +#define _ASM_ARG2L esi +#define _ASM_ARG3L edx +#define _ASM_ARG4L ecx +#define _ASM_ARG5L r8d +#define _ASM_ARG6L r9d + +#define _ASM_ARG1W di +#define _ASM_ARG2W si +#define _ASM_ARG3W dx +#define _ASM_ARG4W cx +#define _ASM_ARG5W r8w +#define _ASM_ARG6W r9w + +#define _ASM_ARG1B dil +#define _ASM_ARG2B sil +#define _ASM_ARG3B dl +#define _ASM_ARG4B cl +#define _ASM_ARG5B r8b +#define _ASM_ARG6B r9b + +#endif + /* * Macros to generate condition code outputs from inline assembly, * The output operand must be type "bool".