From patchwork Sat Nov 9 01:30:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacob Keller X-Patchwork-Id: 13869159 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95CA64437A; Sat, 9 Nov 2024 01:30:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731115841; cv=none; b=quBUj98nqe4eS2iG2F6I4hzf/FlKKDD9iw2+cb5gJ0zAxfpl/p87Od64IQ/e4m4xVpgFDOlmbf/b3jpMgw9cACCG5BOq1MiBdClIb3uML6L/3VR5Hzt7M8TeaslrUpQ/GOs3Ps0Bpel/viHZ8OAM3Dc7ZwOJE5ou47AJnHMiS78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731115841; c=relaxed/simple; bh=3SYvWsFEqn0R64HY4qsiPphPXHioQn9J326+af3bmOY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D/PuhhMfQ6eqE20yBRDlTLNcZeOlZtghfWJucU0Xw4oS8Dfj7O9IzNTn/+mcNQJyCPxHeqRodlYpewWVUdJd9j1y1NueVsEwZj3XL2tbq0HcbOqKDJtQ8abpTMTsmrxPxjx778EvVhEH94TyxtCzz1gehTY6fc4RL0BhDTrtOJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WgMlIo6O; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WgMlIo6O" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731115839; x=1762651839; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=3SYvWsFEqn0R64HY4qsiPphPXHioQn9J326+af3bmOY=; b=WgMlIo6Op1yy0Jh+YDDe4imd2Rgx7cQ49aYZiAref+w3SPKdcyfQCrpr w/hnNyBm60Jt/+Iqel5Jo3xkKogLiEXfWvQxZBJGhOUsxvo9aXpWOaTCn w0iHBiQNRbA+WpQzD5KF2kSj7RrMevG9JH32YDHZh+F69h3n7qZ7Qd1Vn SCjNmlwBYlFDB3m0Y9pdA29NRRf+IaC0pWsjrGDPszTPCVlwyd7S7atmX XTugX0/VzS7O5Y0yhmWZkXFGZbtVj7ZUAlbvmGn5CHN6hYxMpjkq+k2Xt Q9LOVEf+HvEGxtoU/K2KsvY34ScMsVLt9tWJycQk1yxMEs4WFgsGvVe65 w==; X-CSE-ConnectionGUID: zomn14MSQ7mN93tCZh79hQ== X-CSE-MsgGUID: ZIoTR3OtTfWeFPjPyknOBQ== X-IronPort-AV: E=McAfee;i="6700,10204,11250"; a="18637344" X-IronPort-AV: E=Sophos;i="6.12,139,1728975600"; d="scan'208";a="18637344" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2024 17:30:34 -0800 X-CSE-ConnectionGUID: grO9nx2/SNeVr2l/bBe0Xw== X-CSE-MsgGUID: e08N+8dvRbSlVekDlfiZtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="90646192" Received: from jekeller-desk.jf.intel.com ([10.166.241.20]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2024 17:30:33 -0800 From: Jacob Keller Date: Fri, 08 Nov 2024 17:30:21 -0800 Subject: [PATCH net-next v4 8/9] ice: move prefetch enable to ice_setup_rx_ctx Precedence: bulk X-Mailing-List: linux-kbuild@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241108-packing-pack-fields-and-ice-implementation-v4-8-81a9f42c30e5@intel.com> References: <20241108-packing-pack-fields-and-ice-implementation-v4-0-81a9f42c30e5@intel.com> In-Reply-To: <20241108-packing-pack-fields-and-ice-implementation-v4-0-81a9f42c30e5@intel.com> To: Vladimir Oltean , Andrew Morton , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Tony Nguyen , Przemek Kitszel , Masahiro Yamada , netdev Cc: linux-kbuild@vger.kernel.org, Jacob Keller X-Mailer: b4 0.14.1 The ice_write_rxq_ctx() function is responsible for programming the Rx Queue context into hardware. It receives the configuration in unpacked form via the ice_rlan_ctx structure. This function unconditionally modifies the context to set the prefetch enable bit. This was done by commit c31a5c25bb19 ("ice: Always set prefena when configuring an Rx queue"). Setting this bit makes sense, since prefetching descriptors is almost always the preferred behavior. However, the ice_write_rxq_ctx() function is not the place that actually defines the queue context. We initialize the Rx Queue context in ice_setup_rx_ctx(). It is surprising to have the Rx queue context changed by a function who's responsibility is to program the given context to hardware. Following the principle of least surprise, move the setting of the prefetch enable bit out of ice_write_rxq_ctx() and into the ice_setup_rx_ctx(). Signed-off-by: Jacob Keller Reviewed-by: Przemek Kitszel --- drivers/net/ethernet/intel/ice/ice_base.c | 3 +++ drivers/net/ethernet/intel/ice/ice_common.c | 9 +++------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_base.c b/drivers/net/ethernet/intel/ice/ice_base.c index 0a325dec804e..f1fbba19e4e4 100644 --- a/drivers/net/ethernet/intel/ice/ice_base.c +++ b/drivers/net/ethernet/intel/ice/ice_base.c @@ -453,6 +453,9 @@ static int ice_setup_rx_ctx(struct ice_rx_ring *ring) /* Rx queue threshold in units of 64 */ rlan_ctx.lrxqthresh = 1; + /* Enable descriptor prefetch */ + rlan_ctx.prefena = 1; + /* PF acts as uplink for switchdev; set flex descriptor with src_vsi * metadata and flags to allow redirecting to PR netdev */ diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c index a743aede7f59..e31d0ed55dff 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -1430,14 +1430,13 @@ static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, } /** - * ice_write_rxq_ctx + * ice_write_rxq_ctx - Write Rx Queue context to hardware * @hw: pointer to the hardware structure * @rlan_ctx: pointer to the rxq context * @rxq_index: the index of the Rx queue * - * Converts rxq context from sparse to dense structure and then writes - * it to HW register space and enables the hardware to prefetch descriptors - * instead of only fetching them on demand + * Pack the sparse Rx Queue context into dense hardware format and write it + * into the HW register space. */ int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index) @@ -1447,8 +1446,6 @@ int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, if (!rlan_ctx) return -EINVAL; - rlan_ctx->prefena = 1; - ice_pack_rxq_ctx(rlan_ctx, &buf); return ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index);