[v8,15/18] RISC-V: Device, timer, IRQs, and the SBI

Commit Message

Palmer Dabbelt Sept. 13, 2017, 5:01 p.m. UTC

On Wed, 13 Sep 2017 08:36:54 PDT (-0700), Arnd Bergmann wrote:
> On Tue, Sep 12, 2017 at 11:57 PM, Palmer Dabbelt <[e-mail]> wrote:
>
>> +
>> +/* RISC-V TileLink and PCIe share the share address space */
>> +#define PCI_DMA_BUS_IS_PHYS 1
>
> To be pedantic, the comment here is not helpful.

Ya, you're right: TileLink isn't a RISC-V thing, so the comment doesn't even
make sense.

> PCI_DMA_BUS_IS_PHYS is a misnamed symbol that indicates
> the absence of an IOMMU. When it is zero, the scsi and network
> layers assume that they don't need to use bounce buffers
> since the IOMMU can usually address any RAM even if a
> PCI device cannot.

OK.  How does this look?

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Patch

diff --git a/arch/riscv/include/asm/pci.h b/arch/riscv/include/asm/pci.h
index 285747fa2ef0..0f2fc9ef20fc 100644
--- a/arch/riscv/include/asm/pci.h
+++ b/arch/riscv/include/asm/pci.h
@@ -26,7 +26,7 @@ 
 /* RISC-V shim does not initialize PCI bus */
 #define pcibios_assign_all_busses() 1

-/* RISC-V TileLink and PCIe share the share address space */
+/* We do not have an IOMMU */
 #define PCI_DMA_BUS_IS_PHYS 1

 extern int isa_dma_bridge_buggy;