From patchwork Tue May 30 05:37:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolu Lu X-Patchwork-Id: 13259203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E7B6C7EE23 for ; Tue, 30 May 2023 05:40:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230284AbjE3FkR (ORCPT ); Tue, 30 May 2023 01:40:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230315AbjE3Fjr (ORCPT ); Tue, 30 May 2023 01:39:47 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25A7C10C; Mon, 29 May 2023 22:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685425172; x=1716961172; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5i0IWMRYP+ogX9K8FkpBx7ImnE4r1Jowb3nahAxxTSQ=; b=AnQvXiaRHwSBaSktRP1HDgXEJS5qagTdbtUAzyCzaitb7V/amNJv0bOX BJCY8aRok/vKNVvLj2HlEZLi+yeVKcA+sNQmydEoXN1OsdrP7kZSppyQE OUXrnNITpZJd83nuEEWq0f/Y3z9xBHtEr2BI9AteDHKVpM1xXLx3bO7R3 0o4WchEEPAW1hbeza/PGMHn3US7iZJqMyB0rS9+0IXwNx9n9I8bp5Vkf9 WpI8bFLldrh5OM95vG2veYNhsCOQdZXSn+F0bDueakBOxUDWRJthGkACM llb9oH9uiVS/7BlZax9cfDlwMnYA98WmqhI9uPDTtsfAG+RfpHVs2vQbd Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="420579732" X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="420579732" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2023 22:38:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="739369620" X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="739369620" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orsmga001.jf.intel.com with ESMTP; 29 May 2023 22:38:47 -0700 From: Lu Baolu To: Jason Gunthorpe , Kevin Tian , Joerg Roedel , Will Deacon , Robin Murphy , Jean-Philippe Brucker , Nicolin Chen , Yi Liu , Jacob Pan Cc: iommu@lists.linux.dev, linux-kselftest@vger.kernel.org, virtualization@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [RFC PATCHES 07/17] iommufd: Add iommu page fault data Date: Tue, 30 May 2023 13:37:14 +0800 Message-Id: <20230530053724.232765-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530053724.232765-1-baolu.lu@linux.intel.com> References: <20230530053724.232765-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org For user to handle IO page faults generated by IOMMU hardware when walking the HWPT managed by the user. One example of the use case is nested translation, where the first-stage page table is managed by the user space. When allocating a user HWPT, the user could opt-in a flag named IOMMU_HWPT_ALLOC_FLAGS_IOPF_CAPABLE, which indicates that user is capable of handling IO page faults generated for this HWPT. The user also needs to allocate an eventfd and input it in event_fd field of iommu_hwpt_alloc data. On a successful return of hwpt allocation, the user can listen to the event fd and retrieve the page faults by reading from the fd returned at out_fault_fd. The format of the page fault data is encoded in the format defined by struct iommu_hwpt_pgfault. The iommu_hwpt_pgfault is mostly like the iommu_fault with some new members like fault data size and the device object id where the page fault was originated from. Signed-off-by: Lu Baolu --- include/uapi/linux/iommufd.h | 44 +++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index e10e6f74cdf4..2c7c44c00da2 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -444,7 +444,11 @@ struct iommu_hwpt_arm_smmuv3 { /** * struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC) * @size: sizeof(struct iommu_hwpt_alloc) - * @flags: Must be 0 + * @flags: Combination of IOMMU_HWPT_ALLOC_FLAGS_ flags + * - IOPF_CAPABLE: User is capable of handling IO page faults. @event_fd + * must be valid once this flag is set. On successful return, user can + * listen to @event_fd and retrieve faults by reading @out_fault_fd. + * The fault data is encoded in the format defined by iommu_hwpt_pgfault. * @dev_id: The device to allocate this HWPT for * @pt_id: The IOAS to connect this HWPT to * @out_hwpt_id: The ID of the new HWPT @@ -482,6 +486,7 @@ struct iommu_hwpt_arm_smmuv3 { struct iommu_hwpt_alloc { __u32 size; __u32 flags; +#define IOMMU_HWPT_ALLOC_FLAGS_IOPF_CAPABLE (1 << 0) __u32 dev_id; __u32 pt_id; __u32 out_hwpt_id; @@ -489,6 +494,8 @@ struct iommu_hwpt_alloc { __u32 hwpt_type; __u32 data_len; __aligned_u64 data_uptr; + __u32 event_fd; + __u32 out_fault_fd; }; #define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC) @@ -705,6 +712,41 @@ struct iommu_hwpt_invalidate { }; #define IOMMU_HWPT_INVALIDATE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_INVALIDATE) +/** + * struct iommu_hwpt_pgfault - iommu page fault data + * @size: sizeof(struct iommu_hwpt_pgfault) + * @flags: Combination of IOMMU_PGFAULT_FLAGS_ flags. + * - PASID_VALID: @pasid field is valid + * - LAST_PAGE: the last page fault in a group + * - PRIV_DATA: @private_data field is valid + * - RESP_NEEDS_PASID: the page response must have the same + * PASID value as the page request. + * @dev_id: id of the originated device + * @pasid: Process Address Space ID + * @grpid: Page Request Group Index + * @perm: requested page permissions (IOMMU_PGFAULT_PERM_* values) + * @addr: page address + * @private_data: device-specific private information + */ +struct iommu_hwpt_pgfault { + __u32 size; + __u32 flags; +#define IOMMU_PGFAULT_FLAGS_PASID_VALID (1 << 0) +#define IOMMU_PGFAULT_FLAGS_LAST_PAGE (1 << 1) +#define IOMMU_PGFAULT_FLAGS_PRIV_DATA (1 << 2) +#define IOMMU_PGFAULT_FLAGS_RESP_NEEDS_PASID (1 << 3) + __u32 dev_id; + __u32 pasid; + __u32 grpid; + __u32 perm; +#define IOMMU_PGFAULT_PERM_READ (1 << 0) +#define IOMMU_PGFAULT_PERM_WRITE (1 << 1) +#define IOMMU_PGFAULT_PERM_EXEC (1 << 2) +#define IOMMU_PGFAULT_PERM_PRIV (1 << 3) + __u64 addr; + __u64 private_data[2]; +}; + /** * struct iommu_device_set_data - ioctl(IOMMU_DEVICE_SET_DATA) * @size: sizeof(struct iommu_device_set_data)