| Message ID | 20230921075431.125239-8-yi.l.liu@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add Intel VT-d nested translation | expand |
On 2023/9/21 21:33, Baolu Lu wrote: > On 2023/9/21 15:54, Yi Liu wrote: >> This adds the data structure for flushing iotlb for the nested domain >> allocated with IOMMU_HWPT_TYPE_VTD_S1 type. >> >> This only supports invalidating IOTLB, but no for device-TLB as device-TLB >> invalidation will be covered automatically in the IOTLB invalidation if the >> underlying IOMMU driver has enabled ATS for the affected device. >> >> Signed-off-by: Yi Liu <yi.l.liu@intel.com> >> --- >> include/uapi/linux/iommufd.h | 34 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 34 insertions(+) >> >> diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h >> index 18a502e206c3..3050efbceb57 100644 >> --- a/include/uapi/linux/iommufd.h >> +++ b/include/uapi/linux/iommufd.h >> @@ -510,6 +510,40 @@ struct iommu_hw_info { >> }; >> #define IOMMU_GET_HW_INFO _IO(IOMMUFD_TYPE, IOMMUFD_CMD_GET_HW_INFO) >> +/** >> + * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d >> + * stage-1 cache invalidation >> + * @IOMMU_VTD_QI_FLAGS_LEAF: The LEAF flag indicates whether only the >> + * leaf PTE caching needs to be invalidated >> + * and other paging structure caches can be >> + * preserved. >> + */ >> +enum iommu_hwpt_vtd_s1_invalidate_flags { >> + IOMMU_VTD_QI_FLAGS_LEAF = 1 << 0, >> +}; >> + >> +/** >> + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation >> + * (IOMMU_HWPT_TYPE_VTD_S1) >> + * @addr: The start address of the addresses to be invalidated. > > Is there an alignment requirement for @addr? If so, is 4K alignment > sufficient? Perhaps we need to document it here so that user space can > calculate the @addr correctly. yes, it should be aligned. let's document it in the kdoc. > >> + * @npages: Number of contiguous 4K pages to be invalidated. >> + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags >> + * @__reserved: Must be 0 >> + * >> + * The Intel VT-d specific invalidation data for user-managed stage-1 cache >> + * invalidation under nested translation. Userspace uses this structure to >> + * tell host about the impacted caches after modifying the stage-1 page >> table. >> + * >> + * Invalidating all the caches related to the page table by setting @addr >> + * to be 0 and @npages to be __aligned_u64(-1). >> + */ >> +struct iommu_hwpt_vtd_s1_invalidate { >> + __aligned_u64 addr; >> + __aligned_u64 npages; >> + __u32 flags; >> + __u32 __reserved; >> +}; >> + >> /** >> * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) >> * @size: sizeof(struct iommu_hwpt_invalidate) > > Best regards, > baolu
> From: Liu, Yi L <yi.l.liu@intel.com> > Sent: Thursday, September 21, 2023 3:54 PM > > +/** > + * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d > + * stage-1 cache invalidation > + * @IOMMU_VTD_QI_FLAGS_LEAF: The LEAF flag indicates whether only the > + * leaf PTE caching needs to be invalidated > + * and other paging structure caches can be > + * preserved. > + */ > +enum iommu_hwpt_vtd_s1_invalidate_flags { > + IOMMU_VTD_QI_FLAGS_LEAF = 1 << 0, > +}; QI is iommu driver internal term. let's use IOMMU_VTD_INV_FLAGS_LEAF here. > + > +/** > + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation > + * (IOMMU_HWPT_TYPE_VTD_S1) > + * @addr: The start address of the addresses to be invalidated. > + * @npages: Number of contiguous 4K pages to be invalidated. > + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags > + * @__reserved: Must be 0 > + * > + * The Intel VT-d specific invalidation data for user-managed stage-1 cache > + * invalidation under nested translation. Userspace uses this structure to s/under/in/ > + * tell host about the impacted caches after modifying the stage-1 page > table. "to tell the impacted cache scope..." > + * > + * Invalidating all the caches related to the page table by setting @addr > + * to be 0 and @npages to be __aligned_u64(-1). This should also call out that device TLB is also invalidated by this request if ATS is enabled on the device.
diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 18a502e206c3..3050efbceb57 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -510,6 +510,40 @@ struct iommu_hw_info { }; #define IOMMU_GET_HW_INFO _IO(IOMMUFD_TYPE, IOMMUFD_CMD_GET_HW_INFO) +/** + * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d + * stage-1 cache invalidation + * @IOMMU_VTD_QI_FLAGS_LEAF: The LEAF flag indicates whether only the + * leaf PTE caching needs to be invalidated + * and other paging structure caches can be + * preserved. + */ +enum iommu_hwpt_vtd_s1_invalidate_flags { + IOMMU_VTD_QI_FLAGS_LEAF = 1 << 0, +}; + +/** + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation + * (IOMMU_HWPT_TYPE_VTD_S1) + * @addr: The start address of the addresses to be invalidated. + * @npages: Number of contiguous 4K pages to be invalidated. + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags + * @__reserved: Must be 0 + * + * The Intel VT-d specific invalidation data for user-managed stage-1 cache + * invalidation under nested translation. Userspace uses this structure to + * tell host about the impacted caches after modifying the stage-1 page table. + * + * Invalidating all the caches related to the page table by setting @addr + * to be 0 and @npages to be __aligned_u64(-1). + */ +struct iommu_hwpt_vtd_s1_invalidate { + __aligned_u64 addr; + __aligned_u64 npages; + __u32 flags; + __u32 __reserved; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate)
This adds the data structure for flushing iotlb for the nested domain allocated with IOMMU_HWPT_TYPE_VTD_S1 type. This only supports invalidating IOTLB, but no for device-TLB as device-TLB invalidation will be covered automatically in the IOTLB invalidation if the underlying IOMMU driver has enabled ATS for the affected device. Signed-off-by: Yi Liu <yi.l.liu@intel.com> --- include/uapi/linux/iommufd.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)