Message ID | 20240411-dev-charlie-support_thead_vector_6_9-v1-10-4af9815ec746@rivosinc.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | riscv: Support vendor extensions and xtheadvector | expand |
On Thu, Apr 11, 2024 at 09:11:16PM -0700, Charlie Jenkins wrote: > From: Heiko Stuebner <heiko@sntech.de> > > The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. > > Define constants for those to access the elements in a readable way. > > Acked-by: Guo Ren <guoren@kernel.org> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> You need to sign off on this as the submitter Charlie.
On Fri, Apr 12, 2024 at 12:27:50PM +0100, Conor Dooley wrote: > On Thu, Apr 11, 2024 at 09:11:16PM -0700, Charlie Jenkins wrote: > > From: Heiko Stuebner <heiko@sntech.de> > > > > The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. > > > > Define constants for those to access the elements in a readable way. > > > > Acked-by: Guo Ren <guoren@kernel.org> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > > You need to sign off on this as the submitter Charlie. I wasn't sure, thank you! - Charlie
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..13bc99c995d1 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -215,6 +215,11 @@ #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* VCSR flags */ +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* symbolic CSR names: */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01