From patchwork Thu Apr 11 00:07:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13625135 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D9F4EAF0 for ; Thu, 11 Apr 2024 00:08:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712794099; cv=none; b=c+pzWwTNOYZc027L7Cgvq/p16E2vEwl5RNafB0fEZ35g/4Lo8aRw1Avkl7stWs8KIq7+EkwQN9CrUBcE81zEUtc72gXCyAE0VPpf2FFr+UPfkQCVxjMeREZxZvuUwiNqcj8GKxB87uJfSYEcNrSrp233aDfmqaJ7lPaEO90BlIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712794099; c=relaxed/simple; bh=J8TrFuN//G6PmUvmCaqpAzaTIpoKbVOHs/yKTawHfLc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=n42lnPpISiZH5CApHQpU3MKhC2G0aMqyhDjQuhJH8dl7FKaRdQ+KmAlj/68+cQPtusNnkoccEFfJQZcn9rEa1ELsJJsl6/TxxuktZzMMGzeV8Y4UE4HwLwUyAwurp++UvfLZpbsN3hhbbeBaDvRhpKavQruLxdtcboRsEbkWFgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=EKzIDZcn; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="EKzIDZcn" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1e50a04c317so5585625ad.1 for ; Wed, 10 Apr 2024 17:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712794098; x=1713398898; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ITt+KwUVR5JlR3QMHjofp/8j27l4zwoSN907Yn7Ybbg=; b=EKzIDZcn1xNYIil1rAjOfIRMooZXf9uJaZFlgZjVKLNkZb471gRPTomn43HfSM4cxo FGnok1gSp/7C6BTe3DU8wTSwmTez2XHWV0Mbd2Znov6NKsylyaEO0R1QTgpDMn49zl1Z yMwnUmCjXMkpQRP84QGFt/AyJkSWVR3JqV1A08zGVB1wDQhKZDr4OKYm20JwNqxQqMII nR8aXuRkTC7VFgWv3BPRVzMnIaPYVDrf+5mHVnsuc2OkI1reojK7Znk7sa+4KiMhzk1r KpAZZKIc3uaamWKWyBOJX0nyfFsfXCM1PnXe5FcdLdOyxw0HsBRXnu5kded9gPDv5FpB AWxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712794098; x=1713398898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ITt+KwUVR5JlR3QMHjofp/8j27l4zwoSN907Yn7Ybbg=; b=b8WVBM/dtvtXZ8V2ABBV9an1fNTlvU0fYJroee2L7eArL5d0owj4KMvxTSPj555CoQ ETHA4ZKhtb1+RavhG2hE6SkLmjVR9G+D8af+zZXYaQTGLQ+dMGo+n9XXWJlur0QulyGE 9LSFdsB2eBqV0/hOkt6xG5N317mSavmhKOBFN2eZEmm4iONphYrA+aoIu5kOMYrFyNnL WhyfY8ap4Mqn9mnKT3pZ+QvfKh17egZjKs0OreX1go9mitWehpzpGZ7GMSvHOhZLglAI 1Zlbiqm5ElGX0LvOledtCw01ECAFCyK3u9LoKlY8ufEyn/sdGKeGart3K5bRl+oaE2sj l76w== X-Forwarded-Encrypted: i=1; AJvYcCWBVFI/G8LF289kR9E0tPW9LxuvK9RCxJf6pcCBL0mO5uA9AMkhmp92f2EyN5PgMvI9FsrvdEiZKjPArmLUESstwCg0zvG2c5V+8pp4Fj/t X-Gm-Message-State: AOJu0YweVSeBFJ3glnrsuDMd5wbjYjL/A6IoDdJl+CF9CAkaWVIY+Uev T/nR2weO0K1pNW1XeLcK0gPmm34G4t7M8hWa1qM7yRYq3/yHZ2p7+D5Mnku/P54= X-Google-Smtp-Source: AGHT+IH+Fv4XZX4/gx4XiswGPlN/TrMeCjxrmPnpJT+OZm0Rkqi3ood4AZl0My6G2DmtNin0INwRaA== X-Received: by 2002:a17:902:d510:b0:1e3:c610:597d with SMTP id b16-20020a170902d51000b001e3c610597dmr4245035plg.60.1712794097994; Wed, 10 Apr 2024 17:08:17 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id f7-20020a170902684700b001e3d8a70780sm130351pln.171.2024.04.10.17.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 17:08:16 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Ajay Kaher , Albert Ou , Alexandre Ghiti , Alexey Makhalov , Anup Patel , Atish Patra , Broadcom internal kernel review list , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, Will Deacon , x86@kernel.org Subject: [PATCH v6 04/24] drivers/perf: riscv: Use BIT macro for shifting operations Date: Wed, 10 Apr 2024 17:07:32 -0700 Message-Id: <20240411000752.955910-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240411000752.955910-1-atishp@rivosinc.com> References: <20240411000752.955910-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 It is a good practice to use BIT() instead of (1 << x). Replace the current usages with BIT(). Take this opportunity to replace few (1UL << x) with BIT() as well for consistency. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 20 ++++++++++---------- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ef8311dafb91..4afa2cd01bae 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type { #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF /* Flags defined for config matching function */ -#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) -#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) -#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) -#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) -#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) -#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) -#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) /* Flags defined for counter start function */ -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) /* Flags defined for counter stop function */ -#define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_RESET BIT(0) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 1823ffb25d35..f23501898657 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) cmask = 1; } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); + cmask = BIT(CSR_INSTRET - CSR_CYCLE); } }