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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF00000016.mail.protection.outlook.com (10.167.244.121) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7519.0 via Frontend Transport; Wed, 1 May 2024 14:55:16 +0000 Received: from chalupa-4a00host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 1 May 2024 09:55:15 -0500 From: Manali Shukla To: , CC: , , , , , , , Subject: [PATCH v2 2/5] KVM: SVM: Add Idle HLT intercept support Date: Wed, 1 May 2024 14:54:30 +0000 Message-ID: <20240501145433.4070-3-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240501145433.4070-1-manali.shukla@amd.com> References: <20240501145433.4070-1-manali.shukla@amd.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000016:EE_|DS0PR12MB8199:EE_ X-MS-Office365-Filtering-Correlation-Id: cc4a87ea-12a9-4006-b0bd-08dc69eeb66f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400014|36860700004|1800799015|376005; X-Microsoft-Antispam-Message-Info: aEFKlzsIu9U/8VcPACN2yQeEZw+hZ0PxeqzSLrieU6QuJvaHpscM47Dw2CAwvFbWFIKlSlnhPbvQWT9v94XnJKTS41bRwUagrFKnvAsErKxcixlsDtJItEsKQEezuMUOPdDwKJjkXpej9TngrVTOHAc0BhXgVkyQzfB27j4NiKpLgmllskjtX2gASXdBuZRzefFrtLLD48bxcAgM7+rZoYUR6mLCpm7ymVPFODZfTpZ7TB44Ye/L8j8EFQa80QE0K0o5GWrMWZvF4GkBW6qF4HJQrBzw4fRC97mktdD/uHT2i1OI7BIXD7gGiEivPzP8913jDtRmC1aOcHg4XoQoNO8bEfmtsPpNylAF1LNvHXt/+pVNuB3xG9qNQIrgvVfzZ7GBwK4+FonPefBgOEInu6NbifTu5KPpObyvm0UmaCEMKsyaTlbxczgVVzjtD6uYBhDwwF4RBEdcZax9Ho561B0Nrmm+HSUg+s0JFzhbwEogGuUXhK5iNTtv2ROEbO2Nziaz62Cib2u/mq0P5ZykrwL/8dEsSbkScigi6Kn4CnteP7qMQl+NXhIqHEL6tBjRbwmDftgVSBKoDAQZAFW5wA5qD2+tuE4qhde0bLRzbQ4lyWiIwAAqTEv+eyiEy+5xFBy9ExRsFyBcNpw/1/k6JZgXoIydPgvxVUKENz2z1ClXpJzJMESWDenPDduCEHkmO4RAxt4Z7tPIVseT12VPWoyKVR3VWAp4i3P0HT0uFT0PsQbcUO7P2QmnplKWgepZB/1ZtpOvtDx8QGzdH28ByDZs8Qg+nXukUrUc2qtjHVSki/ezvRdUELXpMn1/fxwnk9qdSmag5TxulvlVKhI0XhPV4sxzjcmySLKlHvPCnkxZGWHjq0CdFamBbDa17ZyA04T8r9OYRp8hdQlhKvRhStIAi4Dzgt/1V6Z94z0JNqK2yjQMHw0gZhLukGSowPdDNZiMQdo6ynqMSfpGwamb6dUcQZIZekKr+egh5KPh5Lvf58alTUBydlPejlzp2iwYEtMqREp/9vLMlr2fe8HPrxyadJwxlcRTn6IBbPORClyZHrvI9r2cEuLu0fiaI3qlRheXpRRjMeTR2kHOS/N0+3sDjtYUgus97RbFXroHR0cX7R8Tdgw7eKUcJjLcSi+2KL8FXXd9aJdkcTSCPlI4Z2FfHkSFN1hbIZPqW2srdZqjXfijNAKYaoIbth575In0Gq0OqWOFFqbEK0NlyGfOfwQrnVjz/83nWVa7yphJ0vgMgz+04l7z0lmTQRogP7DUpo8DGkeLP55mEBcKJRRxGYYPhbugaP5T1i2CdHMHkG3XCBBsB7SucfqdPqi3lPmL X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(82310400014)(36860700004)(1800799015)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2024 14:55:16.3048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc4a87ea-12a9-4006-b0bd-08dc69eeb66f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000016.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8199 From: Manali Shukla Execution of the HLT instruction by a vCPU can be intercepted by the hypervisor by setting the HLT-Intercept Bit in VMCB, thus resulting in a VMEXIT. It can be possible that soon after the VMEXIT, hypervisor observes that there are pending V_INTR and V_NMI events for the vCPU and causes it to perform a VMRUN to service those events. In that case VMEXIT is wasteful. The Idle HLT intercept feature allows for the HLT instruction execution by a vCPU to be intercepted by hypervisor only if there are no pending V_INTR and V_NMI events for the vCPU. The Idle HLT intercept will not be triggerred, when vCPU is expected to have pending events (V_INR and V_NMI). The feature allows the hypervisor to determine whether vCPU is idle and reduces wasteful VMEXITs. Details about Idle HLT intercept can be found in AMD APM [1]. [1]: AMD64 Architecture Programmer's Manual Pub. 24593, April 2024, Vol 2, 15.9 Instruction Intercepts (Table 15-7: IDLE_HLT). https://bugzilla.kernel.org/attachment.cgi?id=306250 Signed-off-by: Manali Shukla --- arch/x86/include/asm/svm.h | 1 + arch/x86/include/uapi/asm/svm.h | 2 ++ arch/x86/kvm/svm/svm.c | 11 ++++++++--- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 728c98175b9c..3a91928a4060 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -116,6 +116,7 @@ enum { INTERCEPT_INVPCID, INTERCEPT_MCOMMIT, INTERCEPT_TLBSYNC, + INTERCEPT_IDLE_HLT = 166, }; diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index 80e1df482337..9910f86a2cef 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -95,6 +95,7 @@ #define SVM_EXIT_CR14_WRITE_TRAP 0x09e #define SVM_EXIT_CR15_WRITE_TRAP 0x09f #define SVM_EXIT_INVPCID 0x0a2 +#define SVM_EXIT_IDLE_HLT 0x0a6 #define SVM_EXIT_NPF 0x400 #define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401 #define SVM_EXIT_AVIC_UNACCELERATED_ACCESS 0x402 @@ -223,6 +224,7 @@ { SVM_EXIT_CR4_WRITE_TRAP, "write_cr4_trap" }, \ { SVM_EXIT_CR8_WRITE_TRAP, "write_cr8_trap" }, \ { SVM_EXIT_INVPCID, "invpcid" }, \ + { SVM_EXIT_IDLE_HLT, "idle-halt" }, \ { SVM_EXIT_NPF, "npf" }, \ { SVM_EXIT_AVIC_INCOMPLETE_IPI, "avic_incomplete_ipi" }, \ { SVM_EXIT_AVIC_UNACCELERATED_ACCESS, "avic_unaccelerated_access" }, \ diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 0f3b59da0d4a..223c670bf986 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1289,8 +1289,12 @@ static void init_vmcb(struct kvm_vcpu *vcpu) svm_set_intercept(svm, INTERCEPT_MWAIT); } - if (!kvm_hlt_in_guest(vcpu->kvm)) - svm_set_intercept(svm, INTERCEPT_HLT); + if (!kvm_hlt_in_guest(vcpu->kvm)) { + if (cpu_feature_enabled(X86_FEATURE_IDLE_HLT)) + svm_set_intercept(svm, INTERCEPT_IDLE_HLT); + else + svm_set_intercept(svm, INTERCEPT_HLT); + } control->iopm_base_pa = __sme_set(iopm_base); control->msrpm_base_pa = __sme_set(__pa(svm->msrpm)); @@ -3291,6 +3295,7 @@ static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = { [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap, [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap, [SVM_EXIT_INVPCID] = invpcid_interception, + [SVM_EXIT_IDLE_HLT] = kvm_emulate_halt, [SVM_EXIT_NPF] = npf_interception, [SVM_EXIT_RSM] = rsm_interception, [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, @@ -3453,7 +3458,7 @@ int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code) return interrupt_window_interception(vcpu); else if (exit_code == SVM_EXIT_INTR) return intr_interception(vcpu); - else if (exit_code == SVM_EXIT_HLT) + else if (exit_code == SVM_EXIT_HLT || exit_code == SVM_EXIT_IDLE_HLT) return kvm_emulate_halt(vcpu); else if (exit_code == SVM_EXIT_NPF) return npf_interception(vcpu);