From patchwork Wed Jul 24 19:13:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13741283 Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 283AA16F26F for ; Wed, 24 Jul 2024 19:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721848454; cv=none; b=udSdHT/DUn+3EWKgph61WKCObgh+O2Md81AHIHPPnfbzEWkyM0KSChfGfOIx2z7CXLPDvtUaFDORdXxLGG/ECDKWgRoYTEFV/YHVI/Je+0tzpLSkP+Ho/QVtBtdpSa+1pJ5spNaQ2ZArp/Z+QrqUQ8uMxfkjLQqQPSDD+iAbwS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721848454; c=relaxed/simple; bh=K+roXVx59nBWzGVd/j10XnzknGtMw9TY/ZlmKWcsED4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TyiCXqR96Z3+SumQCar79KzOkDlBt/m2Hp4j43aaYU+LAxDR1HWjLvHAgA59z2iIdHzBx9+yxol0ivnuNSmyb3V1M7PReZBwCeCfE13Kwu0zy5RyY2tEr2Txz5CQWexQ8il2yzGpBJah/ReoTce0kgErkIna+En0O+qu1zrpJPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=H5PYC/Am; arc=none smtp.client-ip=209.85.215.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="H5PYC/Am" Received: by mail-pg1-f180.google.com with SMTP id 41be03b00d2f7-6c5bcb8e8edso105465a12.2 for ; Wed, 24 Jul 2024 12:14:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1721848451; x=1722453251; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9o2be5FktIdX69DunJPm+I88K7Op3K5NkCKgmd4N1yw=; b=H5PYC/Amy6/GUWlSVVMEa2u7NT43OorMDj7ei1jkDYHT9Ruh5MNIqNLVQq2jkpr9TR lofnP20fd01M+7W/zyiinnpyDdwj1tt3vQZdbwS9CmherBuWSTwCtuu80y00cYT4bv6X hKTUpUJcbx6XxVUc+NrkptWzFMQiOt5w/gKfQ0ZxIB12PhhNiGVxK55zVWEg3ghV/+Iu KDbgudwXSBb/9yk8xyhGFKDgEg+82i0dkZ4ShtXeEgfcNw1cx8BdS1X+PbaPgCU9GBfb xemiAGks0M6pqsCN/qAryyGyVQTzJ3DtyR4QWLhb96LA/oSfnNQJWSBl68HC436n0k/R MvHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721848451; x=1722453251; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9o2be5FktIdX69DunJPm+I88K7Op3K5NkCKgmd4N1yw=; b=c7J3MFYgY57n9Pc8iomOKyWVRTiL0YpoirHsNkMBlwDXOmKF5zCoCYncDXGxE10irU xSjjfGQ9KQoP9hGny95bwRZ5iWerFJwP9tWcNLzvPxTbpQqo7M//Fq6xSX/i58gw4Z9s njG3yg+/Gv1ElMDlB1MCqhaqfID+fVeWMtA4m/Oc0Ugs6ETZ/sOQjSzdYtNX1OZ9TJDs ln/1cl/o2ruZhUTWDkUUsvGgXkWPNmdQH95gx8yn9ohEGt942RcfCJ9RYtv0GXsh0czP 1+t7Pfhfdoaog2upq0i4OdaoxXWAEks/GGRCLy3ioTYkAeXmmEwKPz1Rmuzo1xZoy0m7 uonA== X-Forwarded-Encrypted: i=1; AJvYcCWk5l0YOK+6qENnGl/3xLvEJ2BcquBMegaQjfg/vkJ9FPxnol9vubjYlpOk+Ghnbt91lNcBfDuo99w3FABFbcRcybU9VcMu2jdwBIgYNTba X-Gm-Message-State: AOJu0YygXYg5pmN6zu1frkKfdnozhQkvqneJQ8NLZvZL6t55+WvnO62S QCepkzn80SIdQJ8hQmmxPMcPixEzV9V7b8xdFkhpUT6fZ0CcyEq8kPnAAKtstEs= X-Google-Smtp-Source: AGHT+IGml4Ivlcw1uQn42NekZlDrMhlkGwT4LRZEe7EtL0Hl+DUwkE0/fPanaXbyA4W7vRKnKMR+Tg== X-Received: by 2002:a17:90a:4e0e:b0:2c9:6ad7:659d with SMTP id 98e67ed59e1d1-2cf23774203mr569184a91.6.1721848451539; Wed, 24 Jul 2024 12:14:11 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cdb73edecesm2022359a91.32.2024.07.24.12.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 12:14:10 -0700 (PDT) From: Charlie Jenkins Date: Wed, 24 Jul 2024 12:13:56 -0700 Subject: [PATCH v7 05/13] riscv: vector: Use vlenb from DT for thead Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240724-xtheadvector-v7-5-b741910ada3e@rivosinc.com> References: <20240724-xtheadvector-v7-0-b741910ada3e@rivosinc.com> In-Reply-To: <20240724-xtheadvector-v7-0-b741910ada3e@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721848437; l=4541; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=K+roXVx59nBWzGVd/j10XnzknGtMw9TY/ZlmKWcsED4=; b=UjDuNzfYyF5zRlgN1PdTxsVkwBys3gPJKT6bq25flPVzBBjtn4flYElVd7/ZB9DYCrJVE42S7 Mb3HHI7syJ4CVUi9sjvBXcf3w545tDO/to4aEKz8lUALuV2XEnGcIpi X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins Acked-by: Conor Dooley --- arch/riscv/Kconfig.vendor | 13 ++++++++++ arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/kernel/cpufeature.c | 48 +++++++++++++++++++++++++++++++++++++ arch/riscv/kernel/vector.c | 12 +++++++++- 4 files changed, 74 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 9897442bd44f..b096548fe0ff 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -26,6 +26,19 @@ config RISCV_ISA_VENDOR_EXT_THEAD extensions. Without this option enabled, T-Head vendor extensions will not be detected at boot and their presence not reported to userspace. + If you don't know what to do here, say Y. + +config RISCV_ISA_XTHEADVECTOR + bool "xtheadvector extension support" + depends on RISCV_ISA_VENDOR_EXT_THEAD + depends on RISCV_ISA_V + depends on FPU + default y + help + Say N here if you want to disable all xtheadvector related procedures + in the kernel. This will disable vector for any T-Head board that + contains xtheadvector rather than the standard vector. + If you don't know what to do here, say Y. endmenu diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 45f9c1171a48..28bdeb1005e0 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; +extern u32 thead_vlenb_of; + void riscv_user_isa_enable(void); #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) { \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 041e5e8f8312..bf25215bad24 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -37,6 +37,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; +u32 thead_vlenb_of; + /** * riscv_isa_extension_base() - Get base extension word * @@ -772,6 +774,46 @@ static void __init riscv_fill_vendor_ext_list(int cpu) } } +static int has_thead_homogeneous_vlenb(void) +{ + int cpu; + u32 prev_vlenb = 0; + u32 vlenb; + + /* Ignore thead,vlenb property if xtheavector is not enabled in the kernel */ + if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return 0; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + return -ENOENT; + } + + if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { + of_node_put(cpu_node); + + if (prev_vlenb) + return -ENOENT; + continue; + } + + if (prev_vlenb && vlenb != prev_vlenb) { + of_node_put(cpu_node); + return -ENOENT; + } + + prev_vlenb = vlenb; + of_node_put(cpu_node); + } + + thead_vlenb_of = vlenb; + return 0; +} + static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) { unsigned int cpu; @@ -828,6 +870,12 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) riscv_fill_vendor_ext_list(cpu); } + if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) && + has_thead_homogeneous_vlenb() < 0) { + pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n"); + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; + } + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) return -ENOENT; diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 682b3feee451..9775d6a9c8ee 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) { unsigned long this_vsize; - /* There are 32 vector registers with vlenb length. */ + /* + * There are 32 vector registers with vlenb length. + * + * If the thead,vlenb property was provided by the firmware, use that + * instead of probing the CSRs. + */ + if (thead_vlenb_of) { + this_vsize = thead_vlenb_of * 32; + return 0; + } + riscv_v_enable(); this_vsize = csr_read(CSR_VLENB) * 32; riscv_v_disable();