| Message ID | 20240911-xtheadvector-v10-6-8d3930091246@rivosinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: Add support for xtheadvector | expand |
Charlie Jenkins <charlie@rivosinc.com> 於 2024年9月12日 週四 下午1:57寫道： > > From: Heiko Stuebner <heiko@sntech.de> > > The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. > > Define constants for those to access the elements in a readable way. > > Acked-by: Guo Ren <guoren@kernel.org> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Andy Chiu <andybnac@gmail.com> > --- > arch/riscv/include/asm/csr.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 25966995da04..3eeb07d73065 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -300,6 +300,10 @@ > #define CSR_STIMECMP 0x14D > #define CSR_STIMECMPH 0x15D > > +#define VCSR_VXRM_MASK 3 > +#define VCSR_VXRM_SHIFT 1 > +#define VCSR_VXSAT_MASK 1 > + > /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ > #define CSR_SISELECT 0x150 > #define CSR_SIREG 0x151 > > -- > 2.45.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..3eeb07d73065 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -300,6 +300,10 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151