[v2,07/15] riscv: misaligned: factorize trap handling

Message ID	20250210213549.1867704-8-cleger@rivosinc.com (mailing list archive)
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Headers	show Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E91802512EA for <linux-kselftest@vger.kernel.org>; Mon, 10 Feb 2025 21:36:14 +0000 (UTC) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Samuel Holland <samuel.holland@sifive.com> Subject: [PATCH v2 07/15] riscv: misaligned: factorize trap handling Date: Mon, 10 Feb 2025 22:35:40 +0100 Message-ID: <20250210213549.1867704-8-cleger@rivosinc.com> In-Reply-To: <20250210213549.1867704-1-cleger@rivosinc.com> References: <20250210213549.1867704-1-cleger@rivosinc.com> Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit
Series	riscv: add SBI FWFT misaligned exception delegation support \| expand [v2,00/15] riscv: add SBI FWFT misaligned exception delegation support [v2,01/15] riscv: add Firmware Feature (FWFT) SBI extensions definitions [v2,02/15] riscv: misaligned: request misaligned exception from SBI [v2,03/15] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing [v2,04/15] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed [v2,05/15] riscv: misaligned: move emulated access uniformity check in a function [v2,06/15] riscv: misaligned: add a function to check misalign trap delegability [v2,07/15] riscv: misaligned: factorize trap handling [v2,08/15] riscv: misaligned: enable IRQs while handling misaligned accesses [v2,09/15] riscv: misaligned: use get_user() instead of __get_user() [v2,10/15] Documentation/sysctl: add riscv to unaligned-trap supported archs [v2,11/15] selftests: riscv: add misaligned access testing [v2,12/15] RISC-V: KVM: add SBI extension init()/deinit() functions [v2,13/15] RISC-V: KVM: add SBI extension reset callback [v2,14/15] RISC-V: KVM: add support for FWFT SBI extension [v2,15/15] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG

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20250210213549.1867704-8-cleger@rivosinc.com (mailing list archive)

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From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Shuah Khan <shuah@kernel.org>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org,
	kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org,
	linux-kselftest@vger.kernel.org
Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>,
 Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH v2 07/15] riscv: misaligned: factorize trap handling
Date: Mon, 10 Feb 2025 22:35:40 +0100
Message-ID: <20250210213549.1867704-8-cleger@rivosinc.com>
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Series

riscv: add SBI FWFT misaligned exception delegation support | expand

Commit Message

Clément Léger Feb. 10, 2025, 9:35 p.m. UTC

misaligned accesses traps are not nmi and should be treated as normal
one using irqentry_enter()/exit(). Since both load/store and user/kernel
should use almost the same path and that we are going to add some code
around that, factorize it.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/kernel/traps.c | 49 ++++++++++++++++-----------------------
 1 file changed, 20 insertions(+), 29 deletions(-)

diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 8ff8e8b36524..55d9f3450398 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -198,47 +198,38 @@  asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *re
 DO_ERROR_INFO(do_trap_load_fault,
 	SIGSEGV, SEGV_ACCERR, "load access fault");
 
-asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
+enum misaligned_access_type {
+	MISALIGNED_STORE,
+	MISALIGNED_LOAD,
+};
+
+static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type type)
 {
-	if (user_mode(regs)) {
-		irqentry_enter_from_user_mode(regs);
+	irqentry_state_t state = irqentry_enter(regs);
 
+	if (type ==  MISALIGNED_LOAD) {
 		if (handle_misaligned_load(regs))
 			do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
-			      "Oops - load address misaligned");
-
-		irqentry_exit_to_user_mode(regs);
+				      "Oops - load address misaligned");
 	} else {
-		irqentry_state_t state = irqentry_nmi_enter(regs);
-
-		if (handle_misaligned_load(regs))
+		if (handle_misaligned_store(regs))
 			do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
-			      "Oops - load address misaligned");
-
-		irqentry_nmi_exit(regs, state);
+				      "Oops - store (or AMO) address misaligned");
 	}
+
+	irqentry_exit(regs, state);
 }
 
-asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs *regs)
+asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
 {
-	if (user_mode(regs)) {
-		irqentry_enter_from_user_mode(regs);
-
-		if (handle_misaligned_store(regs))
-			do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
-				"Oops - store (or AMO) address misaligned");
-
-		irqentry_exit_to_user_mode(regs);
-	} else {
-		irqentry_state_t state = irqentry_nmi_enter(regs);
-
-		if (handle_misaligned_store(regs))
-			do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
-				"Oops - store (or AMO) address misaligned");
+	do_trap_misaligned(regs, MISALIGNED_LOAD);
+}
 
-		irqentry_nmi_exit(regs, state);
-	}
+asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs *regs)
+{
+	do_trap_misaligned(regs, MISALIGNED_STORE);
 }
+
 DO_ERROR_INFO(do_trap_store_fault,
 	SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault");
 DO_ERROR_INFO(do_trap_ecall_s,

[v2,07/15] riscv: misaligned: factorize trap handling

Commit Message

Patch