Message ID | 20250317170625.1142870-12-cleger@rivosinc.com (mailing list archive) |
---|---|
State | New |
Headers | show
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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:18 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Samuel Holland <samuel.holland@sifive.com>, Andrew Jones <ajones@ventanamicro.com> Subject: [PATCH v4 11/18] riscv: misaligned: enable IRQs while handling misaligned accesses Date: Mon, 17 Mar 2025 18:06:17 +0100 Message-ID: <20250317170625.1142870-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: <linux-kselftest.vger.kernel.org> List-Subscribe: <mailto:linux-kselftest+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kselftest+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit |
Series |
riscv: add SBI FWFT misaligned exception delegation support
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diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 55d9f3450398..3eecc2addc41 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -206,6 +206,11 @@ enum misaligned_access_type { static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type type) { irqentry_state_t state = irqentry_enter(regs); + bool enable_irqs = !regs_irqs_disabled(regs); + + /* Enable interrupts if they were enabled in the interrupted context. */ + if (enable_irqs) + local_irq_enable(); if (type == MISALIGNED_LOAD) { if (handle_misaligned_load(regs)) @@ -217,6 +222,9 @@ static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type "Oops - store (or AMO) address misaligned"); } + if (enable_irqs) + local_irq_disable(); + irqentry_exit(regs, state); }
We can safely reenable IRQs if they were enabled in the previous context. This allows to access user memory that could potentially trigger a page fault. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/kernel/traps.c | 8 ++++++++ 1 file changed, 8 insertions(+)