[v4,02/18] riscv: sbi: add new SBI error mappings

Message ID	20250317170625.1142870-3-cleger@rivosinc.com (mailing list archive)
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Headers	show Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F1DF195808 for <linux-kselftest@vger.kernel.org>; Mon, 17 Mar 2025 17:08:10 +0000 (UTC) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Samuel Holland <samuel.holland@sifive.com>, Andrew Jones <ajones@ventanamicro.com> Subject: [PATCH v4 02/18] riscv: sbi: add new SBI error mappings Date: Mon, 17 Mar 2025 18:06:08 +0100 Message-ID: <20250317170625.1142870-3-cleger@rivosinc.com> In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit
Series	riscv: add SBI FWFT misaligned exception delegation support \| expand [v4,00/18] riscv: add SBI FWFT misaligned exception delegation support [v4,01/18] riscv: add Firmware Feature (FWFT) SBI extensions definitions [v4,02/18] riscv: sbi: add new SBI error mappings [v4,03/18] riscv: sbi: add FWFT extension interface [v4,04/18] riscv: sbi: add SBI FWFT extension calls [v4,05/18] riscv: misaligned: request misaligned exception from SBI [v4,06/18] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing [v4,07/18] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed [v4,08/18] riscv: misaligned: move emulated access uniformity check in a function [v4,09/18] riscv: misaligned: add a function to check misalign trap delegability [v4,10/18] riscv: misaligned: factorize trap handling [v4,11/18] riscv: misaligned: enable IRQs while handling misaligned accesses [v4,12/18] riscv: misaligned: use get_user() instead of __get_user() [v4,13/18] Documentation/sysctl: add riscv to unaligned-trap supported archs [v4,14/18] selftests: riscv: add misaligned access testing [v4,15/18] RISC-V: KVM: add SBI extension init()/deinit() functions [v4,16/18] RISC-V: KVM: add SBI extension reset callback [v4,17/18] RISC-V: KVM: add support for FWFT SBI extension [v4,18/18] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG

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20250317170625.1142870-3-cleger@rivosinc.com (mailing list archive)

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From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Shuah Khan <shuah@kernel.org>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org,
	kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org,
	linux-kselftest@vger.kernel.org
Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>,
 Samuel Holland <samuel.holland@sifive.com>,
 Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v4 02/18] riscv: sbi: add new SBI error mappings
Date: Mon, 17 Mar 2025 18:06:08 +0100
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Series

riscv: add SBI FWFT misaligned exception delegation support | expand

Commit Message

Clément Léger March 17, 2025, 5:06 p.m. UTC

A few new errors have been added with SBI V3.0, maps them as close as
possible to errno values.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/sbi.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index bb077d0c912f..d11d22717b49 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -536,11 +536,20 @@  static inline int sbi_err_map_linux_errno(int err)
 	case SBI_SUCCESS:
 		return 0;
 	case SBI_ERR_DENIED:
+	case SBI_ERR_DENIED_LOCKED:
 		return -EPERM;
 	case SBI_ERR_INVALID_PARAM:
+	case SBI_ERR_INVALID_STATE:
+	case SBI_ERR_BAD_RANGE:
 		return -EINVAL;
 	case SBI_ERR_INVALID_ADDRESS:
 		return -EFAULT;
+	case SBI_ERR_NO_SHMEM:
+		return -ENOMEM;
+	case SBI_ERR_TIMEOUT:
+		return -ETIME;
+	case SBI_ERR_IO:
+		return -EIO;
 	case SBI_ERR_NOT_SUPPORTED:
 	case SBI_ERR_FAILURE:
 	default:

[v4,02/18] riscv: sbi: add new SBI error mappings

Commit Message

Patch