From patchwork Mon Jan 22 09:58:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Haibo1" X-Patchwork-Id: 13525038 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE38639FE0; Mon, 22 Jan 2024 09:47:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705916875; cv=none; b=Wz/hXO7bvjz9Y23x3ZtKOHX/iN9QExK82nHTG3jMPb4KCHM1GsAMSUfjgZE+aTlJ7QChU9u77rWHp8nXdzG9J13G+AnI2EylBKSGUmCJqvwb+3bm+zNZoeOiSe2xBd6zPxp1NajFU0pa0nf6HK3tSpZOFy3GV0Xq4ojEtmjfIgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705916875; c=relaxed/simple; bh=mb2fHc2A1yGRLtQVrd7AaiUxf4vQwWHkO6NqfvaU2Rg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pMqdtbKS4CvRq9PvpnYFwpApiahnSDkzLWbpDXNBPGSfU4Og2Rvx6uQZZrUgPZ6Slcx7OVNsusmrn0paAxEp44Bbk2/ql0jntV6heNw75jxUg9fDOgh6VJAvhkoHwumWt6jNRRGxaGNKkck2w+lFIVJwHDzOYJqKR2QiWMrsaFQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=C9my5IT9; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C9my5IT9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705916874; x=1737452874; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mb2fHc2A1yGRLtQVrd7AaiUxf4vQwWHkO6NqfvaU2Rg=; b=C9my5IT9xfJdK8NIKNDmP3+2vFxz6z9zey5Oo/drXzr1psEWwDd3TZbn sdpNhCWHAJmcqnCIeGM3eBoEbID3YEDxrXJ4+5UTaMEg4WPUPj5rjEFlE 8Iam6/Ozr/OoKowzxL3voy/StqIH4TWMN2YMc94Zs/dpJ7ESUEXp2mhlf ql46/1qFoRXQSncth+DQzbo6mRWJjGEQP5NtWpKEUQsAOG8eR87dseoQm 7quC0o8lni40NHGbrNK/FFyhA0S7vrTOP7V5CX+gE/F3bs4l4PyUVu5/B 2f1WqNceyoqUOQoK7x0rEirq6EXVK4Ov4aKJZ2NbXhhw4+qL2Kj4ZEzos w==; X-IronPort-AV: E=McAfee;i="6600,9927,10960"; a="22641985" X-IronPort-AV: E=Sophos;i="6.05,211,1701158400"; d="scan'208";a="22641985" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 01:47:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10960"; a="778535568" X-IronPort-AV: E=Sophos;i="6.05,211,1701158400"; d="scan'208";a="778535568" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 01:47:43 -0800 From: Haibo Xu To: Cc: xiaobo55x@gmail.com, ajones@ventanamicro.com, Haibo Xu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Guo Ren , Conor Dooley , Mayuresh Chitale , Daniel Henrique Barboza , wchen , Minda Chen , Jisheng Zhang , Samuel Holland , Sean Christopherson , Peter Xu , Like Xu , Vipin Sharma , Aaron Lewis , Thomas Huth , Maciej Wieczor-Retman , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: [PATCH v5 10/12] KVM: riscv: selftests: Add guest helper to get vcpu id Date: Mon, 22 Jan 2024 17:58:40 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add guest_get_vcpuid() helper to simplify accessing to per-cpu private data. The sscratch CSR was used to store the vcpu id. Signed-off-by: Haibo Xu Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/include/aarch64/processor.h | 4 ---- tools/testing/selftests/kvm/include/kvm_util_base.h | 2 ++ tools/testing/selftests/kvm/lib/riscv/processor.c | 8 ++++++++ 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h index c42d683102c7..16ae0ac01879 100644 --- a/tools/testing/selftests/kvm/include/aarch64/processor.h +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h @@ -226,8 +226,4 @@ void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, struct arm_smccc_res *res); - - -uint32_t guest_get_vcpuid(void); - #endif /* SELFTEST_KVM_PROCESSOR_H */ diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h b/tools/testing/selftests/kvm/include/kvm_util_base.h index 135ae2eb5249..666438113d22 100644 --- a/tools/testing/selftests/kvm/include/kvm_util_base.h +++ b/tools/testing/selftests/kvm/include/kvm_util_base.h @@ -939,4 +939,6 @@ struct ex_regs; typedef void(*exception_handler_fn)(struct ex_regs *); void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler); +uint32_t guest_get_vcpuid(void); + #endif /* SELFTEST_KVM_UTIL_BASE_H */ diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c index efd9ac4b0198..39a1e9902dec 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -316,6 +316,9 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); + /* Setup sscratch for guest_get_vcpuid() */ + vcpu_set_reg(vcpu, RISCV_CSR_REG(sscratch), vcpu_id); + /* Setup default exception vector of guest */ vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap); @@ -436,3 +439,8 @@ void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handle handlers->exception_handlers[1][0] = handler; } + +uint32_t guest_get_vcpuid(void) +{ + return csr_read(CSR_SSCRATCH); +}