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Tue, 7 Sep 2021 09:50:47 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 14/15] firmware: imx: scu-pd: imx8q: add vpu mu resources Date: Tue, 7 Sep 2021 17:49:21 +0800 Message-Id: <1218d5aae916a78f824de89330e4b012deac5156.1631002447.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: X-ClientProxiedBy: SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR02CA0097.apcprd02.prod.outlook.com (2603:1096:4:92::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +bdBOAi0ggcedu37/Gup0uKDoLp27L2PfIrEcoNzbCVyxJwYygjIou5Eoivh4kpSb+4uwSg6NXnk5JJuG4UhocROeViFGE0N6K3Iz2Ukya6q/VjzxI8Y3Jb1xJ6FRumlJip6dwDG8zJmT4SRVfM1R5q4ORryEDc8gNOLYfPjHmA/CnrNkrSteX4rdK+BijXFJGlKaVcMPF0bzPc4ntsocmcD6A3WZ7JVtbtC/GeDHA3RcmDPaz9oqJNdSMztfsMiU0fkBsqbrNo3SlLOXc8QGt/5Cq8/QtZZlypq3eThEt8OlnJ4LrOX6iYgQSE2IgXV0AoKJ8SmIt6vH8UC5b7aSeluJNpXM1Pu48n6egn4J76zHbXSq0e7LNC9wG3WNbPGX9uZBjOtmV5K/DgVSUDZ2a4NH7L3fX9tqdSTl4buaocluTSJulqH1g4ylnrqY8SYYPNxYxUekFjvrSt8NExCxFQn+RAAskERMpEuMnbALG0YfMM/SrTW2psx2c52yNkKwzK4W1HtBIZaygCxyEeZlbNzZLhTUX1sZ0Uv2VjNpYC4OO0Whr/dwi89anqqJQxRlrG4e2Mdf/Cke7Y/QUFtc/Vr+2F+nxPCp4B0/gqV4oHFBLc4uU7hNJsz91qWo6a25JWczVOCHm7NpxFEBamcR692I2HFMPrpOVGxLfrGYB1M0PH1N5Y1lXGFyQY86k1IKHRWH12KD89+nbtgAbvSCfhkb3daL7+UC7D+elMsQylCzXQea68aQjvhbSscpNbpjzKzCZnDe3mzWGWX1InCuoTsKJRlaOS0or1PygtIWGTRZpCXS9DrL5G9Xm+HDFrQfCGXFSWjNeaYiGglTCWxvE/Xd3Q7P+80Ey7bwzhZB1O61eeXVotN5+xA2Co0BHugDZeGObB43Gcv2a6xwLUneQT662pRfNTzVSOD5X2MAdfIZ1Z1r+fFD6d40kgKog0RY4NsilBLWaxEXmNJ4z9LWoSsI+vqW1TQ63w92huDk3nqUHIpkxaKZiXHX+CvlGzWPp4Ya9ww/Sk0Xbcla9W0ngpZAxr2uSDo1VOBWPC0gwU9lvnDVmSc+SklA6ddQ5aWJXZlrK7XGsHTm/uOLDhuJldoKFU6rMWh7ATGWvhZD84KTgxthZ+YiPW2qnPnNgiQgC9eu0NxnVgVWCkFzrrsRWa6Y+2W4ExpDhUYSi4GQ+bmGIoDVXcQKpo1Ar+s8FXq9j8Eo+oUv54lQOyPKxAWXzkwDG18VKJcxMhMDxI+amGtSNIQwDUmH0iuxHSP4M5IgFBbSTkaJnLNxjuaNT5RLvpc1q5GMC5AiSOwYpcQc/Kz/vxFus78Sc/7EvNzrHgS X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: fcd48198-963e-4de8-7649-08d971e4f7aa X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2021 09:50:47.4380 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GBXq5+53uceC9v7y6Cs1dwS9+WCYnlOrCeDb3ij46omdRtYNxb2e8zLh0/G0I09mw6V/14rbCXZuoowO7ExZ2Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0402MB2772 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org the vpu core depends on the mu resources. if they're missed, the vpu can't work. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index ff6569c4a53b..af3d057e6421 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -155,6 +155,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },