From patchwork Tue Aug 3 08:18:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mats.randgaard@tandberg.com X-Patchwork-Id: 116698 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o738JHQ9019869 for ; Tue, 3 Aug 2010 08:19:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755327Ab0HCITI (ORCPT ); Tue, 3 Aug 2010 04:19:08 -0400 Received: from mail179.messagelabs.com ([85.158.139.35]:51557 "HELO mail179.messagelabs.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1755325Ab0HCITB (ORCPT ); Tue, 3 Aug 2010 04:19:01 -0400 X-VirusChecked: Checked X-Env-Sender: mats.randgaard@tandberg.com X-Msg-Ref: server-10.tower-179.messagelabs.com!1280823537!42160600!1 X-StarScan-Version: 6.2.4; banners=-,-,- X-Originating-IP: [62.70.2.252] Received: (qmail 22581 invoked from network); 3 Aug 2010 08:18:57 -0000 Received: from unknown (HELO OSLEXCP11.eu.tandberg.int) (62.70.2.252) by server-10.tower-179.messagelabs.com with SMTP; 3 Aug 2010 08:18:57 -0000 Received: from ultra.eu.tandberg.int ([10.47.1.15]) by OSLEXCP11.eu.tandberg.int with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Aug 2010 10:18:56 +0200 Received: from localhost.localdomain ([10.47.3.203]) by ultra.eu.tandberg.int (8.13.1/8.13.1) with ESMTP id o738Iu7w014796; Tue, 3 Aug 2010 10:18:56 +0200 From: mats.randgaard@tandberg.com To: linux-media@vger.kernel.org Cc: sudhakar.raj@ti.com, Mats Randgaard Subject: [PATCH 2/2] TVP7002: Changed register values. Date: Tue, 3 Aug 2010 10:18:04 +0200 Message-Id: <1280823484-21664-3-git-send-email-mats.randgaard@tandberg.com> X-Mailer: git-send-email 1.6.4.2 In-Reply-To: <1280823484-21664-2-git-send-email-mats.randgaard@tandberg.com> References: <1280823484-21664-1-git-send-email-mats.randgaard@tandberg.com> <1280823484-21664-2-git-send-email-mats.randgaard@tandberg.com> X-OriginalArrivalTime: 03 Aug 2010 08:18:56.0938 (UTC) FILETIME=[84A2B8A0:01CB32E4] Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 03 Aug 2010 08:19:17 +0000 (UTC) diff --git a/drivers/media/video/tvp7002.c b/drivers/media/video/tvp7002.c index 8116cd4..0f2dc98 100644 --- a/drivers/media/video/tvp7002.c +++ b/drivers/media/video/tvp7002.c @@ -127,7 +127,7 @@ static const struct i2c_reg_value tvp7002_init_default[] = { { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE }, { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE }, - { TVP7002_RGB_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, + { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE }, { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE }, { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, { 0x32, 0x18, TVP7002_RESERVED }, @@ -181,7 +181,6 @@ static const struct i2c_reg_value tvp7002_parms_480P[] = { { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE }, { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE }, { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE }, - { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE }, @@ -203,7 +202,6 @@ static const struct i2c_reg_value tvp7002_parms_576P[] = { { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE }, { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE }, - { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE }, @@ -225,7 +223,6 @@ static const struct i2c_reg_value tvp7002_parms_1080I60[] = { { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, - { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, @@ -247,7 +244,6 @@ static const struct i2c_reg_value tvp7002_parms_1080P60[] = { { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE }, - { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, @@ -269,7 +265,6 @@ static const struct i2c_reg_value tvp7002_parms_1080I50[] = { { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE }, { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, - { TVP7002_HPLL_PHASE_SEL, 0x14, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, @@ -291,7 +286,6 @@ static const struct i2c_reg_value tvp7002_parms_720P60[] = { { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, - { TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, @@ -313,7 +307,6 @@ static const struct i2c_reg_value tvp7002_parms_720P50[] = { { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE }, { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE }, { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, - { TVP7002_HPLL_PHASE_SEL, 0x16, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },