From patchwork Fri Nov 12 21:18:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aguirre Rodriguez, Sergio Alberto" X-Patchwork-Id: 320892 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oACLITj8012920 for ; Fri, 12 Nov 2010 21:18:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757245Ab0KLVSR (ORCPT ); Fri, 12 Nov 2010 16:18:17 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:58224 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932399Ab0KLVSJ (ORCPT ); Fri, 12 Nov 2010 16:18:09 -0500 Received: from dlep34.itg.ti.com ([157.170.170.115]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id oACLI7if005920 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 12 Nov 2010 15:18:07 -0600 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id oACLI6ME019147; Fri, 12 Nov 2010 15:18:07 -0600 (CST) Received: from localhost (dtx0091359-ubuntu-1.am.dhcp.ti.com [128.247.79.64]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id oACLI6f18025; Fri, 12 Nov 2010 15:18:06 -0600 (CST) From: Sergio Aguirre To: Laurent Pinchart Cc: linux-media@vger.kernel.org, Sergio Aguirre Subject: [omap3isp RFC][PATCH 10/10] omap3isp: Remove legacy MMU access regs/fields Date: Fri, 12 Nov 2010 15:18:13 -0600 Message-Id: <1289596693-27660-11-git-send-email-saaguirre@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1289596693-27660-1-git-send-email-saaguirre@ti.com> References: <1289596693-27660-1-git-send-email-saaguirre@ti.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 12 Nov 2010 21:18:35 +0000 (UTC) diff --git a/drivers/media/video/isp/ispreg.h b/drivers/media/video/isp/ispreg.h index 9b0d3ad..af4ddaa 100644 --- a/drivers/media/video/isp/ispreg.h +++ b/drivers/media/video/isp/ispreg.h @@ -72,11 +72,6 @@ OMAP3ISP_SBL_REG_OFFSET) #define OMAP3ISP_SBL_REG(offset) (OMAP3ISP_SBL_REG_BASE + (offset)) -#define OMAP3ISP_MMU_REG_OFFSET 0x1400 -#define OMAP3ISP_MMU_REG_BASE (OMAP3ISP_REG_BASE + \ - OMAP3ISP_MMU_REG_OFFSET) -#define OMAP3ISP_MMU_REG(offset) (OMAP3ISP_MMU_REG_BASE + (offset)) - #define OMAP3ISP_CSI2A_REGS1_REG_OFFSET 0x1800 #define OMAP3ISP_CSI2A_REGS1_REG_BASE (OMAP3ISP_REG_BASE + \ OMAP3ISP_CSI2A_REGS1_REG_OFFSET) @@ -458,26 +453,6 @@ #define ISPRSZ_VFILT3130 (0x0A4) #define ISPRSZ_YENH (0x0A8) -/* MMU module registers */ -#define ISPMMU_REVISION (0x000) -#define ISPMMU_SYSCONFIG (0x010) -#define ISPMMU_SYSSTATUS (0x014) -#define ISPMMU_IRQSTATUS (0x018) -#define ISPMMU_IRQENABLE (0x01C) -#define ISPMMU_WALKING_ST (0x040) -#define ISPMMU_CNTL (0x044) -#define ISPMMU_FAULT_AD (0x048) -#define ISPMMU_TTB (0x04C) -#define ISPMMU_LOCK (0x050) -#define ISPMMU_LD_TLB (0x054) -#define ISPMMU_CAM (0x058) -#define ISPMMU_RAM (0x05C) -#define ISPMMU_GFLUSH (0x060) -#define ISPMMU_FLUSH_ENTRY (0x064) -#define ISPMMU_READ_CAM (0x068) -#define ISPMMU_READ_RAM (0x06c) -#define ISPMMU_EMU_FAULT_AD (0x070) - #define ISP_INT_CLR 0xFF113F11 #define ISPPRV_PCR_EN 1 #define ISPPRV_PCR_BUSY (1 << 1) @@ -1299,24 +1274,6 @@ #define ISPCCDC_LSC_INITIAL_Y_MASK 0x3F0000 #define ISPCCDC_LSC_INITIAL_Y_SHIFT 16 -#define ISPMMU_REVISION_REV_MINOR_MASK 0xF -#define ISPMMU_REVISION_REV_MAJOR_SHIFT 0x4 - -#define IRQENABLE_MULTIHITFAULT (1<<4) -#define IRQENABLE_TWFAULT (1<<3) -#define IRQENABLE_EMUMISS (1<<2) -#define IRQENABLE_TRANSLNFAULT (1<<1) -#define IRQENABLE_TLBMISS (1) - -#define ISPMMU_MMUCNTL_MMU_EN (1<<1) -#define ISPMMU_MMUCNTL_TWL_EN (1<<2) -#define ISPMMU_MMUCNTL_EMUTLBUPDATE (1<<3) -#define ISPMMU_AUTOIDLE 0x1 -#define ISPMMU_SIDLEMODE_FORCEIDLE 0 -#define ISPMMU_SIDLEMODE_NOIDLE 1 -#define ISPMMU_SIDLEMODE_SMARTIDLE 2 -#define ISPMMU_SIDLEMODE_SHIFT 3 - /* ----------------------------------------------------------------------------- * CSI2 receiver registers (ES2.0) */