From patchwork Fri Mar 8 14:59:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Kumar K X-Patchwork-Id: 2238281 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id E082E40077 for ; Fri, 8 Mar 2013 14:40:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934213Ab3CHOj7 (ORCPT ); Fri, 8 Mar 2013 09:39:59 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:8636 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932528Ab3CHOj5 (ORCPT ); Fri, 8 Mar 2013 09:39:57 -0500 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MJC00BC1JEKDZ70@mailout1.samsung.com>; Fri, 08 Mar 2013 23:39:56 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 46.DF.17763.C38F9315; Fri, 08 Mar 2013 23:39:56 +0900 (KST) X-AuditID: cbfee690-b7f6b6d000004563-e7-5139f83c78b7 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id AF.5E.03880.B38F9315; Fri, 08 Mar 2013 23:39:55 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MJC00L6XJCX5550@mmp2.samsung.com>; Fri, 08 Mar 2013 23:39:55 +0900 (KST) From: Arun Kumar K To: linux-media@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org Cc: s.nawrocki@samsung.com, kgene.kim@samsung.com, kilyeon.im@samsung.com, arunkk.samsung@gmail.com Subject: [RFC 02/12] exynos-fimc-is: Adding ARCH support for fimc-is Date: Fri, 08 Mar 2013 09:59:15 -0500 Message-id: <1362754765-2651-3-git-send-email-arun.kk@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1362754765-2651-1-git-send-email-arun.kk@samsung.com> References: <1362754765-2651-1-git-send-email-arun.kk@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrELMWRmVeSWpSXmKPExsWyRsSkVtfmh2WgwaS37BYvNt5itzgw+yGr Re+Cq2wWy98vYbbo2bCV1WLG+X1MFofftLM6sHvsnHWX3eP8jIWMHn1bVjF6fN4kF8ASxWWT kpqTWZZapG+XwJUxed8Z1oIDNhXtsz+wNjCeMuhi5OSQEDCROHejgx3CFpO4cG89WxcjF4eQ wFJGiX27lrHAFF1ve8IOkZjOKDF5WjtUVS+TxJ79V8Ha2QQ0JO6deMwKYosIZEpMvD0RrJtZ IFWi4+gpNhBbWMBFYtm0lWBxFgFVick/TzOB2LwCThK3vvQwQmyTk/iw5xHYTE4BZ4mve64z g9hCQDW3b1xhBVksITCZXeLJzlNQgwQkvk0+BGRzACVkJTYdYIaYIylxcMUNlgmMwgsYGVYx iqYWJBcUJ6UXmegVJ+YWl+al6yXn525iBIb36X/PJuxgvHfA+hBjMtC4icxSosn5wPjIK4k3 NDYxNzU2NTOytLQ0JU1YSZxX/pJMoJBAemJJanZqakFqUXxRaU5q8SFGJg5OqQbGnLDpi2uC 4xnjhPV37fqm758V3yqaMCW903n5rvtaxz0PcBcccVsmO2OR32PX0Jk/Lx5b/fbaXUWeCLZ3 q+6VMfz1CTve4TMj2kh5ZdhbwfutH031TU7N2pTv1XQlN1nZNOjQJIsFKZ8WH7b67ZjHVfzm VE2RqV9lDbNuyN3rwXe4JK4VNvxUYinOSDTUYi4qTgQAb3nZfoUCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPIsWRmVeSWpSXmKPExsVy+t9jQV3rH5aBBvvuWVm82HiL3eLA7Ies Fr0LrrJZLH+/hNmiZ8NWVosZ5/cxWRx+087qwO6xc9Zddo/zMxYyevRtWcXo8XmTXABLVAOj TUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7QCUoKZYk5 pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwhrGjMn7zrAWHLCpaJ/9gbWB8ZRBFyMn h4SAicT1tifsELaYxIV769m6GLk4hASmM0pMntYO5fQySezZfxWsik1AQ+LeicesILaIQKbE xNsTWUBsZoFUiY6jp9hAbGEBF4ll01aCxVkEVCUm/zzNBGLzCjhJ3PrSwwixTU7iw55HYDM5 BZwlvu65zgxiCwHV3L5xhXUCI+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ+bmbGMHR80x6 B+OqBotDjAIcjEo8vBWbLAKFWBPLiitzDzFKcDArifDe2GMZKMSbklhZlVqUH19UmpNafIgx GeiqicxSosn5wMjOK4k3NDYxNzU2tTSxMDGzJE1YSZyX8dSTACGB9MSS1OzU1ILUIpgtTByc Ug2MiUIrNa8oHa/i3vd+b2dw3yvxsuecvx3XvfdyTFSoOJ856cY0vTc2fcY7Jr6t82bo1Dn0 PaWsdcIlpQrGq9tNyrdYvehb+kzLP9tZfVX+htaqrFO/FR8dO+C8Jav0hmo+f2J/udOd3y1n r7/5xGY/eXKKpGnf/nn/97zccLfPePJPrz1/JtvKKrEUZyQaajEXFScCAAxC9xbiAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Adds new clocks needed for ISP submodules in the camera subsystem of Exynos5250. Also adds the AUXDATA entry in mach-exynos5-dt.c. Signed-off-by: Arun Kumar K Signed-off-by: Kilyeon Im --- arch/arm/mach-exynos/clock-exynos5.c | 129 ++++++++++++++++++++++++ arch/arm/mach-exynos/include/mach/map.h | 2 + arch/arm/mach-exynos/include/mach/regs-clock.h | 7 ++ arch/arm/mach-exynos/mach-exynos5-dt.c | 2 + 4 files changed, 140 insertions(+) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 4536515..b2c0825 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -28,6 +28,8 @@ #include "common.h" +#define FIMC_IS_NAME "exynos5-fimc-is" + #ifdef CONFIG_PM_SLEEP static struct sleep_save exynos5_clock_save[] = { SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP), @@ -863,6 +865,16 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_gscl_ctrl, .ctrlbit = (1 << 4), }, { + .name = "fimc-is0", + .devname = FIMC_IS_NAME, + .enable = exynos5_clk_ip_isp0_ctrl, + .ctrlbit = (0xFFC << 20) | (0xFF << 0), + }, { + .name = "fimc-is1", + .devname = FIMC_IS_NAME, + .enable = exynos5_clk_ip_isp1_ctrl, + .ctrlbit = (0x3 << 12) | (0x7 << 0) + }, { .name = "csis", .devname = "s5p-mipi-csis.0", .enable = exynos5_clk_ip_gscl_ctrl, @@ -1248,6 +1260,107 @@ static struct clksrc_clk exynos5_clk_sclk_fimd1 = { .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 }, }; +/* For ACLK_400_ISP */ +static struct clksrc_clk exynos5_clk_mout_aclk_400_isp = { + .clk = { + .name = "mout_aclk_400_isp", + .parent = &exynos5_clk_mout_mpll_user.clk, + }, + .sources = &exynos5_clkset_aclk, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 24, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_dout_aclk_400_isp = { + .clk = { + .name = "dout_aclk_400_isp", + .parent = &exynos5_clk_mout_aclk_400_isp.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 20, .size = 3 }, +}; + +static struct clk *exynos5_clkset_aclk_400_isp_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &exynos5_clk_dout_aclk_400_isp.clk, +}; + +static struct clksrc_sources exynos5_clkset_aclk_400_isp = { + .sources = exynos5_clkset_aclk_400_isp_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_400_isp_list), +}; + +static struct clksrc_clk exynos5_clk_aclk_400_isp = { + .clk = { + .name = "aclk_400_isp", + .devname = FIMC_IS_NAME, + }, + .sources = &exynos5_clkset_aclk_400_isp, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 20, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_266_isp = { + .clk = { + .name = "aclk_266_isp", + .devname = FIMC_IS_NAME, + + }, + .sources = &clk_src_gscl_266, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 16, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_266_isp_div0 = { + .clk = { + .name = "aclk_266_isp_div0", + .devname = FIMC_IS_NAME, + .parent = &exynos5_clk_aclk_266_isp.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_266_isp_div1 = { + .clk = { + .name = "aclk_266_isp_div1", + .devname = FIMC_IS_NAME, + .parent = &exynos5_clk_aclk_266_isp.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_266_isp_divmpwm = { + .clk = { + .name = "aclk_266_isp_divmpwm", + .devname = FIMC_IS_NAME, + .parent = &exynos5_clk_aclk_266_isp_div1.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_ISP2, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_400_isp_div0 = { + .clk = { + .name = "aclk_400_isp_div0", + .devname = FIMC_IS_NAME, + .parent = &exynos5_clk_aclk_400_isp.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_400_isp_div1 = { + .clk = { + .name = "aclk_400_isp_div1", + .devname = FIMC_IS_NAME, + .parent = &exynos5_clk_aclk_400_isp.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_266_gscl = { + .clk = { + .name = "aclk_266_gscl", + .parent = &exynos5_clk_aclk_266.clk, + }, + .sources = &clk_src_gscl_266, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 }, +}; + static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { @@ -1299,6 +1412,15 @@ static struct clksrc_clk exynos5_clksrcs[] = { .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 }, }, { .clk = { + .name = "sclk_bayer", + .enable = exynos5_clksrc_mask_gscl_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 12, .size = 4 }, + }, { + .clk = { .name = "sclk_cam0", .enable = exynos5_clksrc_mask_gscl_ctrl, .ctrlbit = (1 << 16), @@ -1367,6 +1489,13 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_mdout_spi1, &exynos5_clk_mdout_spi2, &exynos5_clk_sclk_fimd1, + &exynos5_clk_aclk_400_isp, + &exynos5_clk_aclk_400_isp_div0, + &exynos5_clk_aclk_400_isp_div1, + &exynos5_clk_aclk_266_isp, + &exynos5_clk_aclk_266_isp_div0, + &exynos5_clk_aclk_266_isp_div1, + &exynos5_clk_aclk_266_isp_divmpwm, }; static struct clk *exynos5_clk_cdev[] = { diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 5bfc744..64bd07d 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -125,6 +125,8 @@ #define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 #define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 +#define EXYNOS5_PA_FIMC_IS 0x13000000 + #define EXYNOS5_PA_FIMC_LITE0 0x13C00000 #define EXYNOS5_PA_FIMC_LITE1 0x13C10000 #define EXYNOS5_PA_FIMC_LITE2 0x13C90000 diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index d36ad76..2a09c9f 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -345,6 +345,13 @@ #define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) +#define EXYNOS5_CLKDIV2_RATIO0 EXYNOS_CLKREG(0x10590) +#define EXYNOS5_CLKDIV2_RATIO1 EXYNOS_CLKREG(0x10594) +#define EXYNOS5_CLKDIV4_RATIO EXYNOS_CLKREG(0x105A0) +#define EXYNOS5_CLKDIV_ISP0 EXYNOS_CLKREG(0x0C300) +#define EXYNOS5_CLKDIV_ISP1 EXYNOS_CLKREG(0x0C304) +#define EXYNOS5_CLKDIV_ISP2 EXYNOS_CLKREG(0x0C308) + #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index f6c3223..4df9929 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -114,6 +114,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos5-fimc-lite.1", NULL), OF_DEV_AUXDATA("samsung,exynos5250-fimc-lite", EXYNOS5_PA_FIMC_LITE2, "exynos5-fimc-lite.2", NULL), + OF_DEV_AUXDATA("samsung,exynos5250-fimc-is", EXYNOS5_PA_FIMC_IS, + "exynos5-fimc-is", NULL), {}, };