From patchwork Tue May 14 10:45:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 2565071 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 9AB713FC5A for ; Tue, 14 May 2013 10:47:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753734Ab3ENKqe (ORCPT ); Tue, 14 May 2013 06:46:34 -0400 Received: from mail-pd0-f169.google.com ([209.85.192.169]:38093 "EHLO mail-pd0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753318Ab3ENKqd (ORCPT ); Tue, 14 May 2013 06:46:33 -0400 Received: by mail-pd0-f169.google.com with SMTP id bv13so323331pdb.28 for ; Tue, 14 May 2013 03:46:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=rflcrQlQPoGb/77nia7OtLBjUVHdkgudkMYaZIYajzU=; b=tWwJrvdGK0qlNCBD7cVURGU6CAi+a65LiIUXlcBOw/beKRWAZdIwogwDt2/rwbTYp0 +0xIAVd6ifr/xrl+3K5wlXU20kgK/mdSlqorqvB5+lZrydvAL0r94GE9m24MmdLz/P2C qMyGb4JjJpw7+SOkQfE7uUcTKf+fpkzdtWAgyhW9l+pk+r1fd1lIt/NI4ueIkous7ByO KZMsYV25/iyQqLZhaqn9uSpR9R5JCSHrfBW9j1d1mpb3vsLv06qPsiNmPvcVmv6OwsXf i3Fy/m/HgDeCsemH2dTnx9tUdVBaIkkfDaTsRZ83oLNqddkT1BrYIHxUHr2Dlx6mqJmH 5ldw== X-Received: by 10.68.40.131 with SMTP id x3mr33826723pbk.216.1368528392796; Tue, 14 May 2013 03:46:32 -0700 (PDT) Received: from localhost.localdomain ([59.98.240.128]) by mx.google.com with ESMTPSA id nt2sm17784107pbc.17.2013.05.14.03.46.26 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 14 May 2013 03:46:32 -0700 (PDT) From: Lad Prabhakar To: LMML Cc: LKML , DLOS , "Lad, Prabhakar" , Hans Verkuil , Laurent Pinchart , Mauro Carvalho Chehab , Guennadi Liakhovetski , Sylwester Nawrocki , Sakari Ailus Subject: [PATCH 2/5] media: i2c: tvp7002: rearrange description of structure members Date: Tue, 14 May 2013 16:15:31 +0530 Message-Id: <1368528334-13595-3-git-send-email-prabhakar.csengg@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1368528334-13595-1-git-send-email-prabhakar.csengg@gmail.com> References: <1368528334-13595-1-git-send-email-prabhakar.csengg@gmail.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Lad, Prabhakar This patch rearranges the description of field members of struct tvp7002_config. Also as the all the fields where accepting a value either 0/1, made the members as bool. Signed-off-by: Lad, Prabhakar Cc: Hans Verkuil Cc: Laurent Pinchart Cc: Mauro Carvalho Chehab Cc: Guennadi Liakhovetski Cc: Sylwester Nawrocki Cc: Sakari Ailus Cc: linux-kernel@vger.kernel.org Cc: davinci-linux-open-source@linux.davincidsp.com --- include/media/tvp7002.h | 44 ++++++++++++++++++++------------------------ 1 files changed, 20 insertions(+), 24 deletions(-) diff --git a/include/media/tvp7002.h b/include/media/tvp7002.h index 7123048..fadb6af 100644 --- a/include/media/tvp7002.h +++ b/include/media/tvp7002.h @@ -28,31 +28,27 @@ #define TVP7002_MODULE_NAME "tvp7002" -/* Platform-dependent data - * - * clk_polarity: - * 0 -> data clocked out on rising edge of DATACLK signal - * 1 -> data clocked out on falling edge of DATACLK signal - * hs_polarity: - * 0 -> active low HSYNC output - * 1 -> active high HSYNC output - * sog_polarity: - * 0 -> normal operation - * 1 -> operation with polarity inverted - * vs_polarity: - * 0 -> active low VSYNC output - * 1 -> active high VSYNC output - * fid_polarity: - * 0 -> the field ID output is set to logic 1 for an odd - * field (field 1) and set to logic 0 for an even - * field (field 0). - * 1 -> operation with polarity inverted. +/** + * struct tvp7002_config - Platform dependent data + *@clk_polarity: Clock polarity + * 0 - Data clocked out on rising edge of DATACLK signal + * 1 - Data clocked out on falling edge of DATACLK signal + *@hs_polarity: HSYNC polarity + * 0 - Active low HSYNC output, 1 - Active high HSYNC output + *@vs_polarity: VSYNC Polarity + * 0 - Active low VSYNC output, 1 - Active high VSYNC output + *@fid_polarity: Active-high Field ID polarity. + * 0 - The field ID output is set to logic 1 for an odd field + * (field 1) and set to logic 0 for an even field (field 0). + * 1 - Operation with polarity inverted. + *@sog_polarity: Active high Sync on Green output polarity. + * 0 - Normal operation, 1 - Operation with polarity inverted */ struct tvp7002_config { - u8 clk_polarity; - u8 hs_polarity; - u8 vs_polarity; - u8 fid_polarity; - u8 sog_polarity; + bool clk_polarity; + bool hs_polarity; + bool vs_polarity; + bool fid_polarity; + bool sog_polarity; }; #endif