From patchwork Tue Aug 20 11:00:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 2847019 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 617DCBF546 for ; Tue, 20 Aug 2013 11:03:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9EBD5204AF for ; Tue, 20 Aug 2013 11:03:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AE1F1204D2 for ; Tue, 20 Aug 2013 11:03:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751382Ab3HTLCe (ORCPT ); Tue, 20 Aug 2013 07:02:34 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:38000 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751374Ab3HTLCc (ORCPT ); Tue, 20 Aug 2013 07:02:32 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r7KB2VIm020921; Tue, 20 Aug 2013 06:02:31 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r7KB2ULs022955; Tue, 20 Aug 2013 06:02:30 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Tue, 20 Aug 2013 06:02:30 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r7KB2UAD031477; Tue, 20 Aug 2013 06:02:30 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r7KB2St04955; Tue, 20 Aug 2013 06:02:28 -0500 (CDT) From: Archit Taneja To: , , , CC: , Archit Taneja , Rajendra Nayak , Sricharan R Subject: [PATCH v2 5/6] arm: dra7xx: hwmod data: add VPE hwmod data and ocp_if info Date: Tue, 20 Aug 2013 16:30:56 +0530 Message-ID: <1376996457-17275-6-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1376996457-17275-1-git-send-email-archit@ti.com> References: <1375452223-30524-1-git-send-email-archit@ti.com> <1376996457-17275-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add hwmod data for the VPE IP, this is needed for the IP to be reset during boot, and control the functional clock when the driver needs it via pm_runtime apis. Add the corresponding ocp_if struct and add it DRA7XX's ocp interface list. Cc: Rajendra Nayak Cc: Sricharan R Signed-off-by: Archit Taneja --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index f647998b..181365d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1883,6 +1883,39 @@ static struct omap_hwmod dra7xx_wd_timer2_hwmod = { }, }; +/* + * 'vpe' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_vpe_hwmod_class = { + .name = "vpe", + .sysc = &dra7xx_vpe_sysc, +}; + +/* vpe */ +static struct omap_hwmod dra7xx_vpe_hwmod = { + .name = "vpe", + .class = &dra7xx_vpe_hwmod_class, + .clkdm_name = "vpe_clkdm", + .main_clk = "dpll_core_h23x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; /* * Interfaces @@ -2636,6 +2669,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per3 -> vpe */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_vpe_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_2__l3_instr, &dra7xx_l4_cfg__l3_main_1, @@ -2714,6 +2755,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__vcp2, &dra7xx_l4_per2__vcp2, &dra7xx_l4_wkup__wd_timer2, + &dra7xx_l4_per3__vpe, NULL, };